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target/riscv/cpu.c: redesign register_cpu_props()

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The function is now a no-op for all cpu_init() callers that are setting
a non-zero misa value in set_misa(), since it's no longer used to sync
cpu->cfg props with env->misa_ext bits. Remove it in those cases.

While we're at it, rename the function to match what it's actually
doing: create user properties to set/remove CPU extensions. Make a note
that it will overwrite env->misa_ext with the defaults set by each user
property.

Update the MISA bits comment in cpu.h as well.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-21-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2023-04-06 15:03:51 -03:00 committed by Alistair Francis
parent 4f13abcb2b
commit dd8f244f35
2 changed files with 11 additions and 35 deletions
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41
target/riscv/cpu.c
View File

@ -228,7 +228,7 @@ static const char * const riscv_intr_names[] = {
"reserved"
};
static void register_cpu_props(Object *obj);
static void riscv_cpu_add_user_properties(Object *obj);
const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
{
@ -356,7 +356,6 @@ static void riscv_any_cpu_init(Object *obj)
#endif
set_priv_version(env, PRIV_VERSION_1_12_0);
register_cpu_props(obj);
}
#if defined(TARGET_RISCV64)
@ -365,7 +364,7 @@ static void rv64_base_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, MXL_RV64, 0);
register_cpu_props(obj);
riscv_cpu_add_user_properties(obj);
/* Set latest version of privileged specification */
set_priv_version(env, PRIV_VERSION_1_12_0);
#ifndef CONFIG_USER_ONLY
@ -377,7 +376,6 @@ static void rv64_sifive_u_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_10_0);
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
@ -390,7 +388,6 @@ static void rv64_sifive_e_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_10_0);
cpu->cfg.mmu = false;
#ifndef CONFIG_USER_ONLY
@ -436,7 +433,7 @@ static void rv128_base_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, MXL_RV128, 0);
register_cpu_props(obj);
riscv_cpu_add_user_properties(obj);
/* Set latest version of privileged specification */
set_priv_version(env, PRIV_VERSION_1_12_0);
#ifndef CONFIG_USER_ONLY
@ -449,7 +446,7 @@ static void rv32_base_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, MXL_RV32, 0);
register_cpu_props(obj);
riscv_cpu_add_user_properties(obj);
/* Set latest version of privileged specification */
set_priv_version(env, PRIV_VERSION_1_12_0);
#ifndef CONFIG_USER_ONLY
@ -461,7 +458,6 @@ static void rv32_sifive_u_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_10_0);
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
@ -474,7 +470,6 @@ static void rv32_sifive_e_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_10_0);
cpu->cfg.mmu = false;
#ifndef CONFIG_USER_ONLY
@ -488,7 +483,6 @@ static void rv32_ibex_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_11_0);
cpu->cfg.mmu = false;
#ifndef CONFIG_USER_ONLY
@ -503,7 +497,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_10_0);
cpu->cfg.mmu = false;
#ifndef CONFIG_USER_ONLY
@ -521,7 +514,7 @@ static void riscv_host_cpu_init(Object *obj)
#elif defined(TARGET_RISCV64)
set_misa(env, MXL_RV64, 0);
#endif
register_cpu_props(obj);
riscv_cpu_add_user_properties(obj);
}
#endif
@ -1577,30 +1570,16 @@ static Property riscv_cpu_extensions[] = {
};
/*
* Register CPU props based on env.misa_ext. If a non-zero
* value was set, register only the required cpu->cfg.ext_*
* properties and leave. env.misa_ext = 0 means that we want
* all the default properties to be registered.
* Add CPU properties with user-facing flags.
*
* This will overwrite existing env->misa_ext values with the
* defaults set via riscv_cpu_add_misa_properties().
*/
static void register_cpu_props(Object *obj)
static void riscv_cpu_add_user_properties(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
Property *prop;
DeviceState *dev = DEVICE(obj);
/*
* If misa_ext is not zero, set cfg properties now to
* allow them to be read during riscv_cpu_realize()
* later on.
*/
if (cpu->env.misa_ext != 0) {
/*
* We don't want to set the default riscv_cpu_extensions
* in this case.
*/
return;
}
riscv_cpu_add_misa_properties(obj);
for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {

5
target/riscv/cpu.h
View File

@ -65,10 +65,7 @@
#define RV(x) ((target_ulong)1 << (x - 'A'))
/*
* Consider updating register_cpu_props() when adding
* new MISA bits here.
*/
/* Consider updating misa_ext_cfgs[] when adding new MISA bits here */
#define RVI RV('I')
#define RVE RV('E') /* E and I are mutually exclusive */
#define RVM RV('M')