mirrors/qemu
0
0
Fork 0
mirror of https://github.com/qemu/qemu.git synced 2024-12-03 08:43:38 +08:00
Code Issues Packages Projects Releases Wiki Activity

target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words)

Browse Source 
Introduce the PROT3W opcode (Parallel Rotate 3 Words).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-25-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-02-13 14:46:56 +01:00
parent 71c49f39b9
commit dce4808f74
2 changed files with 29 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
target/mips/tcg/tx79.decode
View File

@ -54,6 +54,7 @@ PEXTUW 011100 ..... ..... ..... 10010 101000 @rs_rt_rd
PCPYLD 011100 ..... ..... ..... 01110 001001 @rs_rt_rd
PAND 011100 ..... ..... ..... 10010 001001 @rs_rt_rd
PXOR 011100 ..... ..... ..... 10011 001001 @rs_rt_rd
PROT3W 011100 00000 ..... ..... 11111 001001 @rt_rd
# MMI3

28
target/mips/tcg/tx79_translate.c
View File

@ -593,3 +593,31 @@ static bool trans_PCPYUD(DisasContext *s, arg_rtype *a)
return true;
}
/* Parallel Rotate 3 Words Left */
static bool trans_PROT3W(DisasContext *ctx, arg_rtype *a)
{
TCGv_i64 ax;
if (a->rd == 0) {
/* nop */
return true;
}
if (a->rt == 0) {
tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
return true;
}
ax = tcg_temp_new_i64();
tcg_gen_mov_i64(ax, cpu_gpr_hi[a->rt]);
tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], ax, cpu_gpr[a->rt], 0, 32);
tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], ax, 0, 32);
tcg_gen_rotri_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], 32);
tcg_temp_free(ax);
return true;
}