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hw/pxa2xx: Convert cp14 perf registers to new scheme
Convert the PXA2xx cp14 perf registers from old-style coprocessor hooks to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
parent
4b6a83fb0c
commit
dc2a9045cf
142
hw/pxa2xx.c
142
hw/pxa2xx.c
@ -324,80 +324,11 @@ static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
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}
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}
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/* Performace Monitoring Registers */
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#define CPPMNC 0 /* Performance Monitor Control register */
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#define CPCCNT 1 /* Clock Counter register */
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#define CPINTEN 4 /* Interrupt Enable register */
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#define CPFLAG 5 /* Overflow Flag register */
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#define CPEVTSEL 8 /* Event Selection register */
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#define CPPMN0 0 /* Performance Count register 0 */
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#define CPPMN1 1 /* Performance Count register 1 */
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#define CPPMN2 2 /* Performance Count register 2 */
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#define CPPMN3 3 /* Performance Count register 3 */
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static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)
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{
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PXA2xxState *s = (PXA2xxState *) opaque;
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switch (reg) {
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case CPPMNC:
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return s->pmnc;
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case CPCCNT:
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if (s->pmnc & 1)
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return qemu_get_clock_ns(vm_clock);
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else
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return 0;
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case CPINTEN:
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case CPFLAG:
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case CPEVTSEL:
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return 0;
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default:
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printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
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break;
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}
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return 0;
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}
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static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm,
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uint32_t value)
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{
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PXA2xxState *s = (PXA2xxState *) opaque;
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switch (reg) {
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case CPPMNC:
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s->pmnc = value;
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break;
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case CPCCNT:
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case CPINTEN:
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case CPFLAG:
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case CPEVTSEL:
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break;
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default:
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printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
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break;
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}
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}
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static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm)
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{
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switch (crm) {
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case 0:
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return pxa2xx_clkpwr_read(opaque, op2, reg, crm);
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case 1:
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return pxa2xx_perf_read(opaque, op2, reg, crm);
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case 2:
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switch (reg) {
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case CPPMN0:
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case CPPMN1:
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case CPPMN2:
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case CPPMN3:
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return 0;
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}
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/* Fall through */
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default:
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printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
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break;
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@ -412,24 +343,71 @@ static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,
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case 0:
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pxa2xx_clkpwr_write(opaque, op2, reg, crm, value);
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break;
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case 1:
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pxa2xx_perf_write(opaque, op2, reg, crm, value);
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break;
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case 2:
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switch (reg) {
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case CPPMN0:
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case CPPMN1:
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case CPPMN2:
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case CPPMN3:
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return;
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}
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/* Fall through */
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default:
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printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
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break;
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}
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}
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static int pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t *value)
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{
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PXA2xxState *s = (PXA2xxState *)ri->opaque;
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*value = s->pmnc;
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return 0;
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}
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static int pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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PXA2xxState *s = (PXA2xxState *)ri->opaque;
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s->pmnc = value;
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return 0;
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}
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static int pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t *value)
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{
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PXA2xxState *s = (PXA2xxState *)ri->opaque;
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if (s->pmnc & 1) {
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*value = qemu_get_clock_ns(vm_clock);
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} else {
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*value = 0;
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}
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return 0;
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}
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static const ARMCPRegInfo pxa_cp_reginfo[] = {
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/* cp14 crn==1: perf registers */
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{ .name = "CPPMNC", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW,
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.readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write },
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{ .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW,
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.readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore },
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{ .name = "CPINTEN", .cp = 14, .crn = 1, .crm = 4, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPFLAG", .cp = 14, .crn = 1, .crm = 5, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPEVTSEL", .cp = 14, .crn = 1, .crm = 8, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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/* cp14 crn==2: performance count registers */
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{ .name = "CPPMN0", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPPMN1", .cp = 14, .crn = 2, .crm = 1, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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REGINFO_SENTINEL
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};
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static void pxa2xx_setup_cp14(PXA2xxState *s)
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{
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define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s);
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}
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#define MDCNFG 0x00 /* SDRAM Configuration register */
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#define MDREFR 0x04 /* SDRAM Refresh Control register */
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#define MSC0 0x08 /* Static Memory Control register 0 */
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@ -2134,6 +2112,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
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vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
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cpu_arm_set_cp_io(&s->cpu->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
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pxa2xx_setup_cp14(s);
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s->mm_base = 0x48000000;
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s->mm_regs[MDMRS >> 2] = 0x00020002;
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@ -2265,6 +2244,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
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vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
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cpu_arm_set_cp_io(&s->cpu->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
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pxa2xx_setup_cp14(s);
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s->mm_base = 0x48000000;
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s->mm_regs[MDMRS >> 2] = 0x00020002;
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