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tcg-sparc: Implement setcond, setcond2.
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Richard Henderson
Blue Swirl
parent
1c086220a6
commit
dbfe80e1ea
@ -194,6 +194,7 @@ static inline int tcg_target_const_match(tcg_target_long val,
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#define INSN_RS2(x) (x)
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#define INSN_ASI(x) ((x) << 5)
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#define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff))
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#define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
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#define INSN_OFF19(x) (((x) >> 2) & 0x07ffff)
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#define INSN_OFF22(x) (((x) >> 2) & 0x3fffff)
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@ -217,6 +218,9 @@ static inline int tcg_target_const_match(tcg_target_long val,
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#define COND_VC 0xf
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#define BA (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2))
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#define MOVCC_ICC (1 << 18)
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#define MOVCC_XCC (1 << 18 | 1 << 12)
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#define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00))
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#define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10))
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#define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01))
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@ -233,6 +237,7 @@ static inline int tcg_target_const_match(tcg_target_long val,
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#define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
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#define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
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#define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
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#define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c))
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#define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25))
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#define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26))
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@ -580,6 +585,109 @@ static void tcg_out_brcond2_i32(TCGContext *s, int cond,
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}
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#endif
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static void tcg_out_setcond_i32(TCGContext *s, int cond, TCGArg ret,
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TCGArg c1, TCGArg c2, int c2const)
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{
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TCGArg t;
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/* For 32-bit comparisons, we can play games with ADDX/SUBX. */
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switch (cond) {
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case TCG_COND_EQ:
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case TCG_COND_NE:
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if (c2 != 0) {
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tcg_out_arithc(s, ret, c1, c2, c2const, ARITH_XOR);
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}
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c1 = TCG_REG_G0, c2 = ret, c2const = 0;
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cond = (cond == TCG_COND_EQ ? TCG_COND_LEU : TCG_COND_LTU);
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break;
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case TCG_COND_GTU:
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case TCG_COND_GEU:
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if (c2const && c2 != 0) {
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tcg_out_movi_imm13(s, TCG_REG_I5, c2);
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c2 = TCG_REG_I5;
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}
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t = c1, c1 = c2, c2 = t, c2const = 0;
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cond = tcg_swap_cond(cond);
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break;
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case TCG_COND_LTU:
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case TCG_COND_LEU:
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break;
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default:
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tcg_out_cmp(s, c1, c2, c2const);
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#if defined(__sparc_v9__) || defined(__sparc_v8plus__)
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tcg_out_movi_imm13(s, ret, 0);
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tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret)
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| INSN_RS1(tcg_cond_to_bcond[cond])
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| MOVCC_ICC | INSN_IMM11(1));
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#else
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t = gen_new_label();
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tcg_out_branch_i32(s, INSN_COND(tcg_cond_to_bcond[cond], 1), t);
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tcg_out_movi_imm13(s, ret, 1);
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tcg_out_movi_imm13(s, ret, 0);
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tcg_out_label(s, t, (tcg_target_long)s->code_ptr);
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#endif
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return;
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}
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tcg_out_cmp(s, c1, c2, c2const);
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if (cond == TCG_COND_LTU) {
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tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDX);
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} else {
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tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBX);
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}
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}
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#if TCG_TARGET_REG_BITS == 64
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static void tcg_out_setcond_i64(TCGContext *s, int cond, TCGArg ret,
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TCGArg c1, TCGArg c2, int c2const)
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{
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tcg_out_cmp(s, c1, c2, c2const);
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tcg_out_movi_imm13(s, ret, 0);
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tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret)
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| INSN_RS1(tcg_cond_to_bcond[cond])
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| MOVCC_XCC | INSN_IMM11(1));
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}
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#else
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static void tcg_out_setcond2_i32(TCGContext *s, int cond, TCGArg ret,
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TCGArg al, TCGArg ah,
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TCGArg bl, int blconst,
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TCGArg bh, int bhconst)
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{
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int lab;
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switch (cond) {
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case TCG_COND_EQ:
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tcg_out_setcond_i32(s, TCG_COND_EQ, TCG_REG_I5, al, bl, blconst);
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tcg_out_setcond_i32(s, TCG_COND_EQ, ret, ah, bh, bhconst);
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tcg_out_arith(s, ret, ret, TCG_REG_I5, ARITH_AND);
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break;
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case TCG_COND_NE:
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tcg_out_setcond_i32(s, TCG_COND_NE, TCG_REG_I5, al, al, blconst);
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tcg_out_setcond_i32(s, TCG_COND_NE, ret, ah, bh, bhconst);
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tcg_out_arith(s, ret, ret, TCG_REG_I5, ARITH_OR);
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break;
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default:
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lab = gen_new_label();
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tcg_out_cmp(s, ah, bh, bhconst);
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tcg_out_branch_i32(s, INSN_COND(tcg_cond_to_bcond[cond], 1), lab);
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tcg_out_movi_imm13(s, ret, 1);
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tcg_out_branch_i32(s, INSN_COND(COND_NE, 1), lab);
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tcg_out_movi_imm13(s, ret, 0);
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tcg_out_setcond_i32(s, tcg_unsigned_cond(cond), ret, al, bl, blconst);
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tcg_out_label(s, lab, (tcg_target_long)s->code_ptr);
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break;
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}
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}
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#endif
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/* Generate global QEMU prologue and epilogue code */
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void tcg_target_qemu_prologue(TCGContext *s)
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{
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@ -1146,12 +1254,22 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
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tcg_out_brcond_i32(s, args[2], args[0], args[1], const_args[1],
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args[3]);
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break;
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case INDEX_op_setcond_i32:
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tcg_out_setcond_i32(s, args[3], args[0], args[1],
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args[2], const_args[2]);
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break;
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#if TCG_TARGET_REG_BITS == 32
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case INDEX_op_brcond2_i32:
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tcg_out_brcond2_i32(s, args[4], args[0], args[1],
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args[2], const_args[2],
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args[3], const_args[3], args[5]);
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break;
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case INDEX_op_setcond2_i32:
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tcg_out_setcond2_i32(s, args[5], args[0], args[1], args[2],
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args[3], const_args[3],
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args[4], const_args[4]);
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break;
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case INDEX_op_add2_i32:
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tcg_out_arithc(s, args[0], args[2], args[4], const_args[4],
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ARITH_ADDCC);
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@ -1257,6 +1375,11 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
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tcg_out_brcond_i64(s, args[2], args[0], args[1], const_args[1],
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args[3]);
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break;
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case INDEX_op_setcond_i64:
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tcg_out_setcond_i64(s, args[3], args[0], args[1],
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args[2], const_args[2]);
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break;
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case INDEX_op_qemu_ld64:
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tcg_out_qemu_ld(s, args, 3);
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break;
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@ -1309,8 +1432,11 @@ static const TCGTargetOpDef sparc_op_defs[] = {
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{ INDEX_op_sar_i32, { "r", "r", "rJ" } },
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{ INDEX_op_brcond_i32, { "r", "rJ" } },
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{ INDEX_op_setcond_i32, { "r", "r", "rJ" } },
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#if TCG_TARGET_REG_BITS == 32
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{ INDEX_op_brcond2_i32, { "r", "r", "rJ", "rJ" } },
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{ INDEX_op_setcond2_i32, { "r", "r", "r", "rJ", "rJ" } },
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{ INDEX_op_add2_i32, { "r", "r", "r", "r", "rJ", "rJ" } },
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{ INDEX_op_sub2_i32, { "r", "r", "r", "r", "rJ", "rJ" } },
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{ INDEX_op_mulu2_i32, { "r", "r", "r", "rJ" } },
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@ -1362,6 +1488,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
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{ INDEX_op_ext32u_i64, { "r", "ri" } },
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{ INDEX_op_brcond_i64, { "r", "rJ" } },
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{ INDEX_op_setcond_i64, { "r", "r", "rJ" } },
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#endif
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{ -1 },
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};
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