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Hexagon (target/hexagon) TCG generation cleanup
Simplify TCG generation of hex_reg_written Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-2-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -35,7 +35,6 @@ static inline TCGv gen_read_preg(TCGv pred, uint8_t num)
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static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot)
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{
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TCGv one = tcg_const_tl(1);
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TCGv zero = tcg_const_tl(0);
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TCGv slot_mask = tcg_temp_new();
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@ -43,12 +42,17 @@ static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot)
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tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero,
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val, hex_new_value[rnum]);
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#if HEX_DEBUG
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/* Do this so HELPER(debug_commit_end) will know */
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tcg_gen_movcond_tl(TCG_COND_EQ, hex_reg_written[rnum], slot_mask, zero,
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one, hex_reg_written[rnum]);
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/*
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* Do this so HELPER(debug_commit_end) will know
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*
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* Note that slot_mask indicates the value is not written
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* (i.e., slot was cancelled), so we create a true/false value before
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* or'ing with hex_reg_written[rnum].
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*/
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tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero);
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tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
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#endif
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tcg_temp_free(one);
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tcg_temp_free(zero);
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tcg_temp_free(slot_mask);
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}
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