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target-mips: add AUI, LSA and PCREL instruction families
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
This commit is contained in:
Leon Alrae
parent
31837be3ee
commit
d4ea6acdf6
42
disas/mips.c
42
disas/mips.c
@ -407,6 +407,12 @@ struct mips_opcode
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"+3" UDI immediate bits 6-20
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"+4" UDI immediate bits 6-25
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R6 immediates/displacements :
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(adding suffix to 'o' to avoid adding new characters)
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"+o" 9 bits immediate/displacement (shift = 7)
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"+o1" 18 bits immediate/displacement (shift = 0)
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"+o2" 19 bits immediate/displacement (shift = 0)
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Other:
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"()" parens surrounding optional value
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"," separates operands
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@ -1217,6 +1223,17 @@ const struct mips_opcode mips_builtin_opcodes[] =
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them first. The assemblers uses a hash table based on the
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instruction name anyhow. */
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/* name, args, match, mask, pinfo, membership */
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{"lwpc", "s,+o2", 0xec080000, 0xfc180000, WR_d, 0, I32R6},
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{"lwupc", "s,+o2", 0xec100000, 0xfc180000, WR_d, 0, I64R6},
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{"ldpc", "s,+o1", 0xec180000, 0xfc1c0000, WR_d, 0, I64R6},
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{"addiupc", "s,+o2", 0xec000000, 0xfc180000, WR_d, 0, I32R6},
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{"auipc", "s,u", 0xec1e0000, 0xfc1f0000, WR_d, 0, I32R6},
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{"aluipc", "s,u", 0xec1f0000, 0xfc1f0000, WR_d, 0, I32R6},
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{"daui", "s,t,u", 0x74000000, 0xfc000000, RD_s|WR_t, 0, I64R6},
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{"dahi", "s,u", 0x04060000, 0xfc1f0000, RD_s, 0, I64R6},
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{"dati", "s,u", 0x041e0000, 0xfc1f0000, RD_s, 0, I64R6},
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{"lsa", "d,s,t", 0x00000005, 0xfc00073f, WR_d|RD_s|RD_t, 0, I32R6},
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{"dlsa", "d,s,t", 0x00000015, 0xfc00073f, WR_d|RD_s|RD_t, 0, I64R6},
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{"clz", "U,s", 0x00000050, 0xfc1f07ff, WR_d|RD_s, 0, I32R6},
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{"clo", "U,s", 0x00000051, 0xfc1f07ff, WR_d|RD_s, 0, I32R6},
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{"dclz", "U,s", 0x00000052, 0xfc1f07ff, WR_d|RD_s, 0, I64R6},
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@ -1822,6 +1839,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 },
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{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3 },
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{"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 },
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{"aui", "s,t,u", 0x3c000000, 0xfc000000, RD_s|WR_t, 0, I32R6},
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{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I5|I33|N55},
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{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
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{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 },
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@ -3645,10 +3663,28 @@ print_insn_args (const char *d,
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break;
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case 'o':
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delta = (l >> OP_SH_DELTA_R6) & OP_MASK_DELTA_R6;
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if (delta & 0x8000) {
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delta |= ~0xffff;
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switch (*(d+1)) {
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case '1':
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d++;
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delta = l & ((1 << 18) - 1);
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if (delta & 0x20000) {
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delta |= ~0x1ffff;
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}
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break;
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case '2':
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d++;
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delta = l & ((1 << 19) - 1);
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if (delta & 0x40000) {
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delta |= ~0x3ffff;
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}
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break;
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default:
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delta = (l >> OP_SH_DELTA_R6) & OP_MASK_DELTA_R6;
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if (delta & 0x8000) {
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delta |= ~0xffff;
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}
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}
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(*info->fprintf_func) (info->stream, "%d", delta);
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break;
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@ -75,6 +75,7 @@ enum {
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OPC_BGTZ = (0x07 << 26),
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OPC_BGTZL = (0x17 << 26),
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OPC_JALX = (0x1D << 26), /* MIPS 16 only */
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OPC_DAUI = (0x1D << 26),
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OPC_JALXS = OPC_JALX | 0x5,
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/* Load and stores */
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OPC_LDL = (0x1A << 26),
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@ -141,8 +142,25 @@ enum {
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/* Cache and prefetch */
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OPC_CACHE = (0x2F << 26),
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OPC_PREF = (0x33 << 26),
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/* Reserved major opcode */
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OPC_MAJOR3B_RESERVED = (0x3B << 26),
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/* PC-relative address computation / loads */
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OPC_PCREL = (0x3B << 26),
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};
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/* PC-relative address computation / loads */
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#define MASK_OPC_PCREL_TOP2BITS(op) (MASK_OP_MAJOR(op) | (op & (3 << 19)))
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#define MASK_OPC_PCREL_TOP5BITS(op) (MASK_OP_MAJOR(op) | (op & (0x1f << 16)))
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enum {
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/* Instructions determined by bits 19 and 20 */
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OPC_ADDIUPC = OPC_PCREL | (0 << 19),
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R6_OPC_LWPC = OPC_PCREL | (1 << 19),
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OPC_LWUPC = OPC_PCREL | (2 << 19),
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/* Instructions determined by bits 16 ... 20 */
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OPC_AUIPC = OPC_PCREL | (0x1e << 16),
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OPC_ALUIPC = OPC_PCREL | (0x1f << 16),
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/* Other */
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R6_OPC_LDPC = OPC_PCREL | (6 << 18),
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};
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/* MIPS special opcodes */
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@ -231,7 +249,6 @@ enum {
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OPC_SPIM = 0x0E | OPC_SPECIAL, /* unofficial */
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OPC_SYNC = 0x0F | OPC_SPECIAL,
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OPC_SPECIAL15_RESERVED = 0x15 | OPC_SPECIAL,
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OPC_SPECIAL28_RESERVED = 0x28 | OPC_SPECIAL,
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OPC_SPECIAL29_RESERVED = 0x29 | OPC_SPECIAL,
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OPC_SPECIAL39_RESERVED = 0x39 | OPC_SPECIAL,
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@ -266,6 +283,9 @@ enum {
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R6_OPC_DCLZ = 0x12 | OPC_SPECIAL,
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R6_OPC_DCLO = 0x13 | OPC_SPECIAL,
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R6_OPC_SDBBP = 0x0e | OPC_SPECIAL,
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OPC_LSA = 0x05 | OPC_SPECIAL,
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OPC_DLSA = 0x15 | OPC_SPECIAL,
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};
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/* Multiplication variants of the vr54xx. */
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@ -309,6 +329,9 @@ enum {
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OPC_TEQI = (0x0C << 16) | OPC_REGIMM,
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OPC_TNEI = (0x0E << 16) | OPC_REGIMM,
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OPC_SYNCI = (0x1F << 16) | OPC_REGIMM,
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OPC_DAHI = (0x06 << 16) | OPC_REGIMM,
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OPC_DATI = (0x1e << 16) | OPC_REGIMM,
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};
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/* Special2 opcodes */
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@ -2162,8 +2185,15 @@ static void gen_logic_imm(DisasContext *ctx, uint32_t opc,
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regnames[rs], uimm);
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break;
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case OPC_LUI:
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tcg_gen_movi_tl(cpu_gpr[rt], imm << 16);
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MIPS_DEBUG("lui %s, " TARGET_FMT_lx, regnames[rt], uimm);
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if (rs != 0 && (ctx->insn_flags & ISA_MIPS32R6)) {
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/* OPC_AUI */
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tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm << 16);
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tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
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MIPS_DEBUG("aui %s, %s, %04x", regnames[rt], regnames[rs], imm);
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} else {
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tcg_gen_movi_tl(cpu_gpr[rt], imm << 16);
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MIPS_DEBUG("lui %s, " TARGET_FMT_lx, regnames[rt], uimm);
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}
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break;
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default:
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@ -2767,6 +2797,77 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
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MIPS_DEBUG("%s %s", opn, regnames[reg]);
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}
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static inline void gen_r6_ld(target_long addr, int reg, int memidx,
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TCGMemOp memop)
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{
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TCGv t0 = tcg_const_tl(addr);
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tcg_gen_qemu_ld_tl(t0, t0, memidx, memop);
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gen_store_gpr(t0, reg);
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tcg_temp_free(t0);
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}
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static inline void gen_pcrel(DisasContext *ctx, int rs, int16_t imm)
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{
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target_long offset;
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target_long addr;
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switch (MASK_OPC_PCREL_TOP2BITS(ctx->opcode)) {
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case OPC_ADDIUPC:
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if (rs != 0) {
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offset = sextract32(ctx->opcode << 2, 0, 21);
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addr = addr_add(ctx, ctx->pc, offset);
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tcg_gen_movi_tl(cpu_gpr[rs], addr);
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}
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break;
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case R6_OPC_LWPC:
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offset = sextract32(ctx->opcode << 2, 0, 21);
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addr = addr_add(ctx, ctx->pc, offset);
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gen_r6_ld(addr, rs, ctx->mem_idx, MO_TESL);
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break;
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#if defined(TARGET_MIPS64)
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case OPC_LWUPC:
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check_mips_64(ctx);
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offset = sextract32(ctx->opcode << 2, 0, 21);
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addr = addr_add(ctx, ctx->pc, offset);
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gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEUL);
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break;
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#endif
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default:
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switch (MASK_OPC_PCREL_TOP5BITS(ctx->opcode)) {
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case OPC_AUIPC:
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if (rs != 0) {
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offset = imm << 16;
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addr = addr_add(ctx, ctx->pc, offset);
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tcg_gen_movi_tl(cpu_gpr[rs], addr);
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}
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break;
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case OPC_ALUIPC:
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if (rs != 0) {
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offset = imm << 16;
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addr = ~0xFFFF & addr_add(ctx, ctx->pc, offset);
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tcg_gen_movi_tl(cpu_gpr[rs], addr);
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}
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break;
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#if defined(TARGET_MIPS64)
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case R6_OPC_LDPC: /* bits 16 and 17 are part of immediate */
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case R6_OPC_LDPC + (1 << 16):
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case R6_OPC_LDPC + (2 << 16):
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case R6_OPC_LDPC + (3 << 16):
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check_mips_64(ctx);
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offset = sextract32(ctx->opcode << 3, 0, 21);
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addr = addr_add(ctx, (ctx->pc & ~0x7), offset);
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gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEQ);
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break;
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#endif
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default:
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MIPS_INVAL("OPC_PCREL");
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generate_exception(ctx, EXCP_RI);
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break;
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}
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break;
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}
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}
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static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
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{
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const char *opn = "r6 mul/div";
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@ -15097,6 +15198,20 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
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op1 = MASK_SPECIAL(ctx->opcode);
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switch (op1) {
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case OPC_LSA:
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if (rd != 0) {
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int imm2 = extract32(ctx->opcode, 6, 3);
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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gen_load_gpr(t0, rs);
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gen_load_gpr(t1, rt);
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tcg_gen_shli_tl(t0, t0, imm2 + 1);
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tcg_gen_add_tl(t0, t0, t1);
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tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
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tcg_temp_free(t1);
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tcg_temp_free(t0);
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}
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break;
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case OPC_MULT ... OPC_DIVU:
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op2 = MASK_R6_MULDIV(ctx->opcode);
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switch (op2) {
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@ -15134,6 +15249,20 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
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generate_exception(ctx, EXCP_DBp);
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break;
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#if defined(TARGET_MIPS64)
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case OPC_DLSA:
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check_mips_64(ctx);
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if (rd != 0) {
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int imm2 = extract32(ctx->opcode, 6, 3);
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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gen_load_gpr(t0, rs);
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gen_load_gpr(t1, rt);
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tcg_gen_shli_tl(t0, t0, imm2 + 1);
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tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
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tcg_temp_free(t1);
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tcg_temp_free(t0);
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}
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break;
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case R6_OPC_DCLO:
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case R6_OPC_DCLZ:
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if (rt == 0 && sa == 1) {
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@ -15319,13 +15448,18 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
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case OPC_TNE:
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gen_trap(ctx, op1, rs, rt, -1);
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break;
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case OPC_PMON: /* Pmon entry point, also R4010 selsl */
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case OPC_LSA: /* OPC_PMON */
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if (ctx->insn_flags & ISA_MIPS32R6) {
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decode_opc_special_r6(env, ctx);
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} else {
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/* Pmon entry point, also R4010 selsl */
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#ifdef MIPS_STRICT_STANDARD
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MIPS_INVAL("PMON / selsl");
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generate_exception(ctx, EXCP_RI);
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MIPS_INVAL("PMON / selsl");
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generate_exception(ctx, EXCP_RI);
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#else
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gen_helper_0e0i(pmon, sa);
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gen_helper_0e0i(pmon, sa);
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#endif
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}
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break;
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case OPC_SYSCALL:
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generate_exception(ctx, EXCP_SYSCALL);
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@ -16297,6 +16431,24 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
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check_dsp(ctx);
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gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2);
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break;
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#if defined(TARGET_MIPS64)
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case OPC_DAHI:
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check_insn(ctx, ISA_MIPS32R6);
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check_mips_64(ctx);
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if (rs != 0) {
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tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 32);
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}
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MIPS_DEBUG("dahi %s, %04x", regnames[rs], imm);
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break;
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case OPC_DATI:
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check_insn(ctx, ISA_MIPS32R6);
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check_mips_64(ctx);
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if (rs != 0) {
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tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 48);
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}
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MIPS_DEBUG("dati %s, %04x", regnames[rs], imm);
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break;
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#endif
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default: /* Invalid */
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MIPS_INVAL("regimm");
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generate_exception(ctx, EXCP_RI);
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@ -16409,7 +16561,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
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gen_slt_imm(ctx, op, rt, rs, imm);
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break;
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case OPC_ANDI: /* Arithmetic with immediate opcode */
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case OPC_LUI:
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case OPC_LUI: /* OPC_AUI */
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case OPC_ORI:
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case OPC_XORI:
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gen_logic_imm(ctx, op, rt, rs, imm);
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@ -16707,14 +16859,37 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
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}
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break;
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#endif
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case OPC_JALX:
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check_insn(ctx, ASE_MIPS16 | ASE_MICROMIPS);
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offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
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gen_compute_branch(ctx, op, 4, rs, rt, offset);
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case OPC_DAUI: /* OPC_JALX */
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if (ctx->insn_flags & ISA_MIPS32R6) {
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#if defined(TARGET_MIPS64)
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/* OPC_DAUI */
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check_mips_64(ctx);
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if (rt != 0) {
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TCGv t0 = tcg_temp_new();
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gen_load_gpr(t0, rs);
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tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16);
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tcg_temp_free(t0);
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}
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MIPS_DEBUG("daui %s, %s, %04x", regnames[rt], regnames[rs], imm);
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#else
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generate_exception(ctx, EXCP_RI);
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MIPS_INVAL("major opcode");
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#endif
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} else {
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/* OPC_JALX */
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check_insn(ctx, ASE_MIPS16 | ASE_MICROMIPS);
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offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
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gen_compute_branch(ctx, op, 4, rs, rt, offset);
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}
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break;
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case OPC_MDMX:
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check_insn(ctx, ASE_MDMX);
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/* MDMX: Not implemented. */
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break;
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case OPC_PCREL:
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check_insn(ctx, ISA_MIPS32R6);
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gen_pcrel(ctx, rs, imm);
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break;
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default: /* Invalid */
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MIPS_INVAL("major opcode");
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generate_exception(ctx, EXCP_RI);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user