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target-arm: Pass mmu_idx to get_phys_addr()
Make all the callers of get_phys_addr() pass it the correct mmu_idx rather than just a simple "is_user" flag. This includes properly decoding the AT/ATS system instructions; we include the logic for handling all the opc1/opc2 cases because we'll need them later for supporting EL2/EL3, even if we don't have the regdef stanzas yet. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
This commit is contained in:
Peter Maydell
parent
060e8a48cb
commit
d364970287
@ -13,7 +13,7 @@
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#ifndef CONFIG_USER_ONLY
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static inline int get_phys_addr(CPUARMState *env, target_ulong address,
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int access_type, int is_user,
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int access_type, ARMMMUIdx mmu_idx,
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hwaddr *phys_ptr, int *prot,
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target_ulong *page_size);
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@ -1459,7 +1459,7 @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
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}
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static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
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int access_type, int is_user)
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int access_type, ARMMMUIdx mmu_idx)
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{
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hwaddr phys_addr;
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target_ulong page_size;
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@ -1467,7 +1467,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
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int ret;
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uint64_t par64;
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ret = get_phys_addr(env, value, access_type, is_user,
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ret = get_phys_addr(env, value, access_type, mmu_idx,
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&phys_addr, &prot, &page_size);
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if (extended_addresses_enabled(env)) {
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/* ret is a DFSR/IFSR value for the long descriptor
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@ -1509,11 +1509,58 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
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static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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{
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int is_user = ri->opc2 & 2;
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int access_type = ri->opc2 & 1;
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uint64_t par64;
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ARMMMUIdx mmu_idx;
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int el = arm_current_el(env);
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bool secure = arm_is_secure_below_el3(env);
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par64 = do_ats_write(env, value, access_type, is_user);
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switch (ri->opc2 & 6) {
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case 0:
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/* stage 1 current state PL1: ATS1CPR, ATS1CPW */
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switch (el) {
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case 3:
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mmu_idx = ARMMMUIdx_S1E3;
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break;
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case 2:
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mmu_idx = ARMMMUIdx_S1NSE1;
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break;
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case 1:
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mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
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break;
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default:
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g_assert_not_reached();
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}
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break;
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case 2:
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/* stage 1 current state PL0: ATS1CUR, ATS1CUW */
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switch (el) {
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case 3:
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mmu_idx = ARMMMUIdx_S1SE0;
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break;
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case 2:
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mmu_idx = ARMMMUIdx_S1NSE0;
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break;
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case 1:
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mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
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break;
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default:
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g_assert_not_reached();
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}
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break;
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case 4:
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/* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
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mmu_idx = ARMMMUIdx_S12NSE1;
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break;
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case 6:
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/* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
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mmu_idx = ARMMMUIdx_S12NSE0;
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break;
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default:
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g_assert_not_reached();
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}
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par64 = do_ats_write(env, value, access_type, mmu_idx);
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A32_BANKED_CURRENT_REG_SET(env, par, par64);
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}
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@ -1521,10 +1568,40 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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int is_user = ri->opc2 & 2;
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int access_type = ri->opc2 & 1;
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ARMMMUIdx mmu_idx;
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int secure = arm_is_secure_below_el3(env);
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env->cp15.par_el[1] = do_ats_write(env, value, access_type, is_user);
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switch (ri->opc2 & 6) {
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case 0:
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switch (ri->opc1) {
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case 0: /* AT S1E1R, AT S1E1W */
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mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
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break;
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case 4: /* AT S1E2R, AT S1E2W */
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mmu_idx = ARMMMUIdx_S1E2;
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break;
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case 6: /* AT S1E3R, AT S1E3W */
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mmu_idx = ARMMMUIdx_S1E3;
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break;
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default:
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g_assert_not_reached();
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}
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break;
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case 2: /* AT S1E0R, AT S1E0W */
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mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
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break;
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case 4: /* AT S12E1R, AT S12E1W */
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mmu_idx = ARMMMUIdx_S12NSE1;
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break;
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case 6: /* AT S12E0R, AT S12E0W */
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mmu_idx = ARMMMUIdx_S12NSE0;
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break;
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default:
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g_assert_not_reached();
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}
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env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
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}
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#endif
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@ -5144,13 +5221,13 @@ static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
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* @env: CPUARMState
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* @address: virtual address to get physical address for
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* @access_type: 0 for read, 1 for write, 2 for execute
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* @is_user: 0 for privileged access, 1 for user
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* @mmu_idx: MMU index indicating required translation regime
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* @phys_ptr: set to the physical address corresponding to the virtual address
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* @prot: set to the permissions for the page containing phys_ptr
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* @page_size: set to the size of the page containing phys_ptr
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*/
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static inline int get_phys_addr(CPUARMState *env, target_ulong address,
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int access_type, int is_user,
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int access_type, ARMMMUIdx mmu_idx,
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hwaddr *phys_ptr, int *prot,
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target_ulong *page_size)
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{
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@ -5159,6 +5236,11 @@ static inline int get_phys_addr(CPUARMState *env, target_ulong address,
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*/
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uint32_t sctlr = A32_BANKED_CURRENT_REG_GET(env, sctlr);
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/* This will go away when we handle mmu_idx properly here */
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int is_user = (mmu_idx == ARMMMUIdx_S12NSE0 ||
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mmu_idx == ARMMMUIdx_S1SE0 ||
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mmu_idx == ARMMMUIdx_S1NSE0);
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/* Fast Context Switch Extension. */
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if (address < 0x02000000) {
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address += A32_BANKED_CURRENT_REG_GET(env, fcseidr);
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@ -5194,13 +5276,11 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
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hwaddr phys_addr;
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target_ulong page_size;
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int prot;
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int ret, is_user;
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int ret;
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uint32_t syn;
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bool same_el = (arm_current_el(env) != 0);
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/* TODO: pass the translation regime to get_phys_addr */
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is_user = (arm_mmu_idx_to_el(mmu_idx) == 0);
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ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
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ret = get_phys_addr(env, address, access_type, mmu_idx, &phys_addr, &prot,
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&page_size);
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if (ret == 0) {
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/* Map a single [sub]page. */
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@ -5236,12 +5316,14 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
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hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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hwaddr phys_addr;
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target_ulong page_size;
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int prot;
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int ret;
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ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size);
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ret = get_phys_addr(env, addr, 0, cpu_mmu_index(env), &phys_addr,
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&prot, &page_size);
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if (ret != 0) {
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return -1;
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