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hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read()
Implement icv_nmiar1_read() for icc_nmiar1_read(), so add definition for ICH_LR_EL2.NMI and ICH_AP1R_EL2.NMI bit. If FEAT_GICv3_NMI is supported, ich_ap_write() should consider ICV_AP1R_EL1.NMI bit. In icv_activate_irq() and icv_eoir_write(), the ICV_AP1R_EL1.NMI bit should be set or clear according to the Non-maskable property. And the RPR priority should also update the NMI bit according to the APR priority NMI bit. By the way, add gicv3_icv_nmiar1_read trace event. If the hpp irq is a NMI, the icv iar read should return 1022 and trap for NMI again Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [PMM: use cs->nmi_support instead of cs->gic->nmi_support] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-20-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
parent
28cca59c46
commit
d2c0c6aab6
@ -158,6 +158,10 @@ static int ich_highest_active_virt_prio(GICv3CPUState *cs)
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int i;
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int aprmax = ich_num_aprs(cs);
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if (cs->ich_apr[GICV3_G1NS][0] & ICV_AP1R_EL1_NMI) {
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return 0x0;
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}
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for (i = 0; i < aprmax; i++) {
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uint32_t apr = cs->ich_apr[GICV3_G0][i] |
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cs->ich_apr[GICV3_G1NS][i];
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@ -192,6 +196,7 @@ static int hppvi_index(GICv3CPUState *cs)
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* correct behaviour.
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*/
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int prio = 0xff;
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bool nmi = false;
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if (!(cs->ich_vmcr_el2 & (ICH_VMCR_EL2_VENG0 | ICH_VMCR_EL2_VENG1))) {
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/* Both groups disabled, definitely nothing to do */
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@ -200,6 +205,7 @@ static int hppvi_index(GICv3CPUState *cs)
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for (i = 0; i < cs->num_list_regs; i++) {
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uint64_t lr = cs->ich_lr_el2[i];
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bool thisnmi;
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int thisprio;
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if (ich_lr_state(lr) != ICH_LR_EL2_STATE_PENDING) {
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@ -218,10 +224,12 @@ static int hppvi_index(GICv3CPUState *cs)
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}
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}
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thisnmi = lr & ICH_LR_EL2_NMI;
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thisprio = ich_lr_prio(lr);
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if (thisprio < prio) {
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if ((thisprio < prio) || ((thisprio == prio) && (thisnmi & (!nmi)))) {
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prio = thisprio;
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nmi = thisnmi;
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idx = i;
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}
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}
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@ -290,6 +298,7 @@ static bool icv_hppi_can_preempt(GICv3CPUState *cs, uint64_t lr)
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* equivalent of these checks.
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*/
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int grp;
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bool is_nmi;
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uint32_t mask, prio, rprio, vpmr;
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if (!(cs->ich_hcr_el2 & ICH_HCR_EL2_EN)) {
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@ -302,10 +311,11 @@ static bool icv_hppi_can_preempt(GICv3CPUState *cs, uint64_t lr)
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*/
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prio = ich_lr_prio(lr);
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is_nmi = lr & ICH_LR_EL2_NMI;
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vpmr = extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT,
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ICH_VMCR_EL2_VPMR_LENGTH);
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if (prio >= vpmr) {
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if (!is_nmi && prio >= vpmr) {
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/* Priority mask masks this interrupt */
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return false;
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}
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@ -327,6 +337,11 @@ static bool icv_hppi_can_preempt(GICv3CPUState *cs, uint64_t lr)
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return true;
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}
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if ((prio & mask) == (rprio & mask) && is_nmi &&
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!(cs->ich_apr[GICV3_G1NS][0] & ICV_AP1R_EL1_NMI)) {
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return true;
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}
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return false;
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}
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@ -551,7 +566,11 @@ static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
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trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
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cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU;
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if (cs->nmi_support) {
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cs->ich_apr[grp][regno] = value & (0xFFFFFFFFU | ICV_AP1R_EL1_NMI);
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} else {
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cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU;
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}
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gicv3_cpuif_virt_irq_fiq_update(cs);
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return;
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@ -698,7 +717,11 @@ static void icv_ctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static uint64_t icv_rpr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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int prio = ich_highest_active_virt_prio(cs);
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uint64_t prio = ich_highest_active_virt_prio(cs);
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if (cs->ich_apr[GICV3_G1NS][0] & ICV_AP1R_EL1_NMI) {
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prio |= ICV_RPR_EL1_NMI;
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}
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trace_gicv3_icv_rpr_read(gicv3_redist_affid(cs), prio);
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return prio;
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@ -737,13 +760,19 @@ static void icv_activate_irq(GICv3CPUState *cs, int idx, int grp)
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*/
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uint32_t mask = icv_gprio_mask(cs, grp);
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int prio = ich_lr_prio(cs->ich_lr_el2[idx]) & mask;
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bool nmi = cs->ich_lr_el2[idx] & ICH_LR_EL2_NMI;
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int aprbit = prio >> (8 - cs->vprebits);
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int regno = aprbit / 32;
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int regbit = aprbit % 32;
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cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT;
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cs->ich_lr_el2[idx] |= ICH_LR_EL2_STATE_ACTIVE_BIT;
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cs->ich_apr[grp][regno] |= (1 << regbit);
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if (nmi) {
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cs->ich_apr[grp][regno] |= ICV_AP1R_EL1_NMI;
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} else {
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cs->ich_apr[grp][regno] |= (1 << regbit);
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}
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}
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static void icv_activate_vlpi(GICv3CPUState *cs)
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@ -764,6 +793,7 @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri)
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int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS;
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int idx = hppvi_index(cs);
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uint64_t intid = INTID_SPURIOUS;
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int el = arm_current_el(env);
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if (idx == HPPVI_INDEX_VLPI) {
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if (cs->hppvlpi.grp == grp && icv_hppvlpi_can_preempt(cs)) {
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@ -773,11 +803,16 @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri)
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} else if (idx >= 0) {
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uint64_t lr = cs->ich_lr_el2[idx];
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int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0;
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bool nmi = env->cp15.sctlr_el[el] & SCTLR_NMI && lr & ICH_LR_EL2_NMI;
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if (thisgrp == grp && icv_hppi_can_preempt(cs, lr)) {
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intid = ich_lr_vintid(lr);
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if (!gicv3_intid_is_special(intid)) {
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icv_activate_irq(cs, idx, grp);
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if (!nmi) {
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icv_activate_irq(cs, idx, grp);
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} else {
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intid = INTID_NMI;
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}
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} else {
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/* Interrupt goes from Pending to Invalid */
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cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT;
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@ -798,8 +833,37 @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri)
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static uint64_t icv_nmiar1_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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/* todo */
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GICv3CPUState *cs = icc_cs_from_env(env);
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int idx = hppvi_index(cs);
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uint64_t intid = INTID_SPURIOUS;
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if (idx >= 0 && idx != HPPVI_INDEX_VLPI) {
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uint64_t lr = cs->ich_lr_el2[idx];
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int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0;
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if ((thisgrp == GICV3_G1NS) && icv_hppi_can_preempt(cs, lr)) {
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intid = ich_lr_vintid(lr);
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if (!gicv3_intid_is_special(intid)) {
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if (lr & ICH_LR_EL2_NMI) {
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icv_activate_irq(cs, idx, GICV3_G1NS);
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} else {
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intid = INTID_SPURIOUS;
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}
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} else {
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/* Interrupt goes from Pending to Invalid */
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cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT;
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/*
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* We will now return the (bogus) ID from the list register,
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* as per the pseudocode.
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*/
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}
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}
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}
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trace_gicv3_icv_nmiar1_read(gicv3_redist_affid(cs), intid);
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gicv3_cpuif_virt_update(cs);
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return intid;
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}
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@ -1424,7 +1488,7 @@ static void icv_increment_eoicount(GICv3CPUState *cs)
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ICH_HCR_EL2_EOICOUNT_LENGTH, eoicount + 1);
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}
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static int icv_drop_prio(GICv3CPUState *cs)
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static int icv_drop_prio(GICv3CPUState *cs, bool *nmi)
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{
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/* Drop the priority of the currently active virtual interrupt
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* (favouring group 0 if there is a set active bit at
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@ -1446,6 +1510,12 @@ static int icv_drop_prio(GICv3CPUState *cs)
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continue;
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}
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if (i == 0 && cs->nmi_support && (*papr1 & ICV_AP1R_EL1_NMI)) {
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*papr1 &= (~ICV_AP1R_EL1_NMI);
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*nmi = true;
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return 0xff;
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}
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/* We can't just use the bit-twiddling hack icc_drop_prio() does
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* because we need to return the bit number we cleared so
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* it can be compared against the list register's priority field.
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@ -1505,6 +1575,7 @@ static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri,
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int irq = value & 0xffffff;
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int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS;
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int idx, dropprio;
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bool nmi = false;
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trace_gicv3_icv_eoir_write(ri->crm == 8 ? 0 : 1,
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gicv3_redist_affid(cs), value);
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@ -1517,8 +1588,8 @@ static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri,
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* error checks" (because that lets us avoid scanning the AP
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* registers twice).
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*/
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dropprio = icv_drop_prio(cs);
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if (dropprio == 0xff) {
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dropprio = icv_drop_prio(cs, &nmi);
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if (dropprio == 0xff && !nmi) {
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/* No active interrupt. It is CONSTRAINED UNPREDICTABLE
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* whether the list registers are checked in this
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* situation; we choose not to.
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@ -1540,8 +1611,9 @@ static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t lr = cs->ich_lr_el2[idx];
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int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0;
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int lr_gprio = ich_lr_prio(lr) & icv_gprio_mask(cs, grp);
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bool thisnmi = lr & ICH_LR_EL2_NMI;
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if (thisgrp == grp && lr_gprio == dropprio) {
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if (thisgrp == grp && (lr_gprio == dropprio || (thisnmi & nmi))) {
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if (!icv_eoi_split(env, cs) || irq >= GICV3_LPI_INTID_START) {
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/*
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* Priority drop and deactivate not split: deactivate irq now.
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@ -2627,7 +2699,11 @@ static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
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trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
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cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU;
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if (cs->nmi_support) {
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cs->ich_apr[grp][regno] = value & (0xFFFFFFFFU | ICV_AP1R_EL1_NMI);
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} else {
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cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU;
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}
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gicv3_cpuif_virt_irq_fiq_update(cs);
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}
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@ -2744,6 +2820,11 @@ static void ich_lr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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8 - cs->vpribits, 0);
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}
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/* Enforce RES0 bit in NMI field when FEAT_GICv3_NMI is not implemented */
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if (!cs->nmi_support) {
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value &= ~ICH_LR_EL2_NMI;
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}
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cs->ich_lr_el2[regno] = value;
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gicv3_cpuif_virt_update(cs);
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}
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@ -246,6 +246,7 @@ FIELD(GICR_VPENDBASER, VALID, 63, 1)
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#define ICH_LR_EL2_PRIORITY_SHIFT 48
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#define ICH_LR_EL2_PRIORITY_LENGTH 8
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#define ICH_LR_EL2_PRIORITY_MASK (0xffULL << ICH_LR_EL2_PRIORITY_SHIFT)
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#define ICH_LR_EL2_NMI (1ULL << 59)
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#define ICH_LR_EL2_GROUP (1ULL << 60)
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#define ICH_LR_EL2_HW (1ULL << 61)
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#define ICH_LR_EL2_STATE_SHIFT 62
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@ -277,6 +278,9 @@ FIELD(GICR_VPENDBASER, VALID, 63, 1)
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#define ICH_VTR_EL2_PREBITS_SHIFT 26
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#define ICH_VTR_EL2_PRIBITS_SHIFT 29
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#define ICV_AP1R_EL1_NMI (1ULL << 63)
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#define ICV_RPR_EL1_NMI (1ULL << 63)
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/* ITS Registers */
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FIELD(GITS_BASER, SIZE, 0, 8)
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@ -152,6 +152,7 @@ gicv3_icv_rpr_read(uint32_t cpu, uint64_t val) "GICv3 ICV_RPR read cpu 0x%x valu
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gicv3_icv_hppir_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_HPPIR%d read cpu 0x%x value 0x%" PRIx64
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gicv3_icv_dir_write(uint32_t cpu, uint64_t val) "GICv3 ICV_DIR write cpu 0x%x value 0x%" PRIx64
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gicv3_icv_iar_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_IAR%d read cpu 0x%x value 0x%" PRIx64
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gicv3_icv_nmiar1_read(uint32_t cpu, uint64_t val) "GICv3 ICV_NMIAR1 read cpu 0x%x value 0x%" PRIx64
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gicv3_icv_eoir_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_EOIR%d write cpu 0x%x value 0x%" PRIx64
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gicv3_cpuif_virt_update(uint32_t cpuid, int idx, int hppvlpi, int grp, int prio) "GICv3 CPU i/f 0x%x virt HPPI update LR index %d HPPVLPI %d grp %d prio %d"
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gicv3_cpuif_virt_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel) "GICv3 CPU i/f 0x%x virt HPPI update: setting FIQ %d IRQ %d"
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