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Parallel NOR Flash patches queue
- Code movement to ease maintainability - Tracing improvements -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmBTdUwACgkQ4+MsLN6t wN4JkBAA29h2uDZC3CYCy6ydq0vQy1ATQRlG9b8JrLEO4fJ3JLDWIHXJzOhDK2q7 Q+pV0ZaCYt8n8ciRgAGX2+EbNWZDuw8KVaO7vdWEvRcTUp67YY/Q2bFWMQP5vS9/ rcW0HY0xjYJZ5QxXeBXY8LHWDKlLu1JNLg3K1jGy/QyjRVowuD2lwLqlI4l6ldYX +D3ZP97zAlv64pnyuJ3ttGePHbiB5D4KtEwiMShMzMjcEj4+t8klD+YEKbRsO7rO cSCIRRrQGdy0BnTRR9tWkVxuRgSQAn0brLSR/UAGosI6IBSTVtQVmG3HVZ4LyJrm fXYlXbyzVlplxcwcnFQLnrJkJ4btH4hBYRLSYUe4uxN1azJOF0KcuJ9UTCQLaby2 QHD7gsA0IDXT2clekLIQC1EELSF9wNIcoVIEy85OCcFHVfHCZWIRojLdvcFLWHBQ O6TY3TwndAa3RNj7gnU8co5fPpUVQtdLKxj3OvD25XPa8u4abMuhx0c+uSW7WQWd Mc4tR8N77TGcLTdDQR7jZJudXRscG8duEqRzE62XZSM0b6FOvuGmsS+usTw8kekQ RNjzSa6Bt4VKuAyEFHWwGuFnaepDUbUjimiuXvT50qxBHFEZ2OJjS/4FZAdAWZVn r/xLgj9BGhyz5mLdNrqaY/ZKy9GqCS5HZuW+ZEp+m52ZVJb40bc= =SW99 -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/philmd/tags/pflash-20210318' into staging Parallel NOR Flash patches queue - Code movement to ease maintainability - Tracing improvements # gpg: Signature made Thu 18 Mar 2021 15:44:12 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd/tags/pflash-20210318: hw/block/pflash_cfi: Replace DPRINTF with trace events hw/block/pflash_cfi01: Correct the type of PFlashCFI01.ro hw/block/pflash_cfi01: Clarify trace events hw/block/pflash_cfi02: Add DeviceReset method hw/block/pflash_cfi02: Factor out pflash_reset_state_machine() hw/block/pflash_cfi02: Rename register_memory(true) as mode_read_array hw/block/pflash_cfi02: Open-code pflash_register_memory(rom=false) hw/block/pflash_cfi02: Set rom_mode to true in pflash_setup_mappings() hw/block/pflash_cfi02: Extract pflash_cfi02_fill_cfi_table() hw/block/pflash_cfi01: Extract pflash_cfi01_fill_cfi_table() hw/block/pflash_cfi: Fix code style for checkpatch.pl Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
cf6b56d4f2
@ -56,16 +56,6 @@
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#include "sysemu/runstate.h"
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#include "trace.h"
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/* #define PFLASH_DEBUG */
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#ifdef PFLASH_DEBUG
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#define DPRINTF(fmt, ...) \
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do { \
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fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__); \
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} while (0)
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#else
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#define DPRINTF(fmt, ...) do { } while (0)
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#endif
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#define PFLASH_BE 0
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#define PFLASH_SECURE 1
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@ -82,7 +72,7 @@ struct PFlashCFI01 {
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uint8_t max_device_width; /* max device width in bytes */
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uint32_t features;
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uint8_t wcycle; /* if 0, the flash is read normally */
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int ro;
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bool ro;
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uint8_t cmd;
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uint8_t status;
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uint16_t ident0;
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@ -115,7 +105,8 @@ static const VMStateDescription vmstate_pflash = {
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}
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};
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/* Perform a CFI query based on the bank width of the flash.
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/*
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* Perform a CFI query based on the bank width of the flash.
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* If this code is called we know we have a device_width set for
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* this flash.
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*/
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@ -125,7 +116,8 @@ static uint32_t pflash_cfi_query(PFlashCFI01 *pfl, hwaddr offset)
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uint32_t resp = 0;
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hwaddr boff;
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/* Adjust incoming offset to match expected device-width
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/*
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* Adjust incoming offset to match expected device-width
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* addressing. CFI query addresses are always specified in terms of
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* the maximum supported width of the device. This means that x8
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* devices and x8/x16 devices in x8 mode behave differently. For
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@ -141,7 +133,8 @@ static uint32_t pflash_cfi_query(PFlashCFI01 *pfl, hwaddr offset)
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if (boff >= sizeof(pfl->cfi_table)) {
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return 0;
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}
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/* Now we will construct the CFI response generated by a single
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/*
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* Now we will construct the CFI response generated by a single
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* device, then replicate that for all devices that make up the
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* bus. For wide parts used in x8 mode, CFI query responses
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* are different than native byte-wide parts.
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@ -152,10 +145,8 @@ static uint32_t pflash_cfi_query(PFlashCFI01 *pfl, hwaddr offset)
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* wider part.
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*/
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if (pfl->device_width != 1 || pfl->bank_width > 4) {
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DPRINTF("%s: Unsupported device configuration: "
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"device_width=%d, max_device_width=%d\n",
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__func__, pfl->device_width,
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pfl->max_device_width);
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trace_pflash_unsupported_device_configuration(pfl->name,
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pfl->device_width, pfl->max_device_width);
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return 0;
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}
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/* CFI query data is repeated, rather than zero padded for
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@ -185,7 +176,8 @@ static uint32_t pflash_devid_query(PFlashCFI01 *pfl, hwaddr offset)
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uint32_t resp;
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hwaddr boff;
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/* Adjust incoming offset to match expected device-width
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/*
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* Adjust incoming offset to match expected device-width
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* addressing. Device ID read addresses are always specified in
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* terms of the maximum supported width of the device. This means
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* that x8 devices and x8/x16 devices in x8 mode behave
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@ -198,21 +190,22 @@ static uint32_t pflash_devid_query(PFlashCFI01 *pfl, hwaddr offset)
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boff = offset >> (ctz32(pfl->bank_width) +
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ctz32(pfl->max_device_width) - ctz32(pfl->device_width));
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/* Mask off upper bits which may be used in to query block
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/*
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* Mask off upper bits which may be used in to query block
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* or sector lock status at other addresses.
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* Offsets 2/3 are block lock status, is not emulated.
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*/
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switch (boff & 0xFF) {
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case 0:
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resp = pfl->ident0;
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trace_pflash_manufacturer_id(resp);
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trace_pflash_manufacturer_id(pfl->name, resp);
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break;
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case 1:
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resp = pfl->ident1;
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trace_pflash_device_id(resp);
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trace_pflash_device_id(pfl->name, resp);
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break;
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default:
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trace_pflash_device_info(offset);
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trace_pflash_device_info(pfl->name, offset);
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return 0;
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}
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/* Replicate responses for each device in bank. */
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@ -260,10 +253,9 @@ static uint32_t pflash_data_read(PFlashCFI01 *pfl, hwaddr offset,
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}
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break;
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default:
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DPRINTF("BUG in %s\n", __func__);
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abort();
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}
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trace_pflash_data_read(offset, width, ret);
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trace_pflash_data_read(pfl->name, offset, width, ret);
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return ret;
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}
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@ -277,7 +269,7 @@ static uint32_t pflash_read(PFlashCFI01 *pfl, hwaddr offset,
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switch (pfl->cmd) {
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default:
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/* This should never happen : reset state & treat it as a read */
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DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
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trace_pflash_read_unknown_state(pfl->name, pfl->cmd);
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pfl->wcycle = 0;
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/*
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* The command 0x00 is not assigned by the CFI open standard,
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@ -297,7 +289,8 @@ static uint32_t pflash_read(PFlashCFI01 *pfl, hwaddr offset,
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case 0x60: /* Block /un)lock */
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case 0x70: /* Status Register */
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case 0xe8: /* Write block */
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/* Status register read. Return status from each device in
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/*
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* Status register read. Return status from each device in
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* bank.
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*/
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ret = pfl->status;
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@ -308,12 +301,13 @@ static uint32_t pflash_read(PFlashCFI01 *pfl, hwaddr offset,
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shift += pfl->device_width * 8;
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}
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} else if (!pfl->device_width && width > 2) {
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/* Handle 32 bit flash cases where device width is not
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/*
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* Handle 32 bit flash cases where device width is not
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* set. (Existing behavior before device width added.)
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*/
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ret |= pfl->status << 16;
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}
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DPRINTF("%s: status %x\n", __func__, ret);
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trace_pflash_read_status(pfl->name, ret);
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break;
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case 0x90:
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if (!pfl->device_width) {
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@ -328,19 +322,20 @@ static uint32_t pflash_read(PFlashCFI01 *pfl, hwaddr offset,
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switch (boff) {
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case 0:
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ret = pfl->ident0 << 8 | pfl->ident1;
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trace_pflash_manufacturer_id(ret);
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trace_pflash_manufacturer_id(pfl->name, ret);
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break;
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case 1:
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ret = pfl->ident2 << 8 | pfl->ident3;
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trace_pflash_device_id(ret);
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trace_pflash_device_id(pfl->name, ret);
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break;
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default:
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trace_pflash_device_info(boff);
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trace_pflash_device_info(pfl->name, boff);
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ret = 0;
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break;
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}
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} else {
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/* If we have a read larger than the bank_width, combine multiple
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/*
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* If we have a read larger than the bank_width, combine multiple
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* manufacturer/device ID queries into a single response.
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*/
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int i;
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@ -367,7 +362,8 @@ static uint32_t pflash_read(PFlashCFI01 *pfl, hwaddr offset,
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ret = 0;
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}
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} else {
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/* If we have a read larger than the bank_width, combine multiple
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/*
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* If we have a read larger than the bank_width, combine multiple
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* CFI queries into a single response.
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*/
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int i;
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@ -380,7 +376,7 @@ static uint32_t pflash_read(PFlashCFI01 *pfl, hwaddr offset,
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break;
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}
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trace_pflash_io_read(offset, width, ret, pfl->cmd, pfl->wcycle);
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trace_pflash_io_read(pfl->name, offset, width, ret, pfl->cmd, pfl->wcycle);
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return ret;
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}
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@ -410,7 +406,7 @@ static inline void pflash_data_write(PFlashCFI01 *pfl, hwaddr offset,
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{
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uint8_t *p = pfl->storage;
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trace_pflash_data_write(offset, width, value, pfl->counter);
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trace_pflash_data_write(pfl->name, offset, width, value, pfl->counter);
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switch (width) {
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case 1:
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p[offset] = value;
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@ -449,7 +445,7 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset,
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cmd = value;
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trace_pflash_io_write(offset, width, value, pfl->wcycle);
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trace_pflash_io_write(pfl->name, offset, width, value, pfl->wcycle);
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if (!pfl->wcycle) {
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/* Set the device in I/O access mode */
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memory_region_rom_device_set_romd(&pfl->mem, false);
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@ -463,14 +459,13 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset,
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goto mode_read_array;
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case 0x10: /* Single Byte Program */
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case 0x40: /* Single Byte Program */
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DPRINTF("%s: Single Byte Program\n", __func__);
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trace_pflash_write(pfl->name, "single byte program (0)");
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break;
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case 0x20: /* Block erase */
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p = pfl->storage;
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offset &= ~(pfl->sector_len - 1);
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DPRINTF("%s: block erase at " TARGET_FMT_plx " bytes %x\n",
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__func__, offset, (unsigned)pfl->sector_len);
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trace_pflash_write_block_erase(pfl->name, offset, pfl->sector_len);
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if (!pfl->ro) {
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memset(p + offset, 0xff, pfl->sector_len);
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@ -481,25 +476,25 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset,
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pfl->status |= 0x80; /* Ready! */
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break;
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case 0x50: /* Clear status bits */
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DPRINTF("%s: Clear status bits\n", __func__);
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trace_pflash_write(pfl->name, "clear status bits");
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pfl->status = 0x0;
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goto mode_read_array;
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case 0x60: /* Block (un)lock */
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DPRINTF("%s: Block unlock\n", __func__);
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trace_pflash_write(pfl->name, "block unlock");
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break;
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case 0x70: /* Status Register */
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DPRINTF("%s: Read status register\n", __func__);
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trace_pflash_write(pfl->name, "read status register");
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pfl->cmd = cmd;
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return;
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case 0x90: /* Read Device ID */
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DPRINTF("%s: Read Device information\n", __func__);
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trace_pflash_write(pfl->name, "read device information");
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pfl->cmd = cmd;
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return;
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case 0x98: /* CFI query */
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DPRINTF("%s: CFI query\n", __func__);
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trace_pflash_write(pfl->name, "CFI query");
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break;
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case 0xe8: /* Write to buffer */
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DPRINTF("%s: Write to buffer\n", __func__);
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trace_pflash_write(pfl->name, "write to buffer");
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/* FIXME should save @offset, @width for case 1+ */
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qemu_log_mask(LOG_UNIMP,
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"%s: Write to buffer emulation is flawed\n",
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@ -507,10 +502,10 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset,
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pfl->status |= 0x80; /* Ready! */
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break;
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case 0xf0: /* Probe for AMD flash */
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DPRINTF("%s: Probe for AMD flash\n", __func__);
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trace_pflash_write(pfl->name, "probe for AMD flash");
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goto mode_read_array;
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case 0xff: /* Read Array */
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DPRINTF("%s: Read array mode\n", __func__);
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trace_pflash_write(pfl->name, "read array mode");
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goto mode_read_array;
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default:
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goto error_flash;
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@ -522,7 +517,7 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset,
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switch (pfl->cmd) {
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case 0x10: /* Single Byte Program */
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case 0x40: /* Single Byte Program */
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DPRINTF("%s: Single Byte Program\n", __func__);
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trace_pflash_write(pfl->name, "single byte program (1)");
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if (!pfl->ro) {
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pflash_data_write(pfl, offset, value, width, be);
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pflash_update(pfl, offset, width);
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@ -544,7 +539,8 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset,
|
||||
|
||||
break;
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case 0xe8:
|
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/* Mask writeblock size based on device width, or bank width if
|
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/*
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* Mask writeblock size based on device width, or bank width if
|
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* device width not specified.
|
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*/
|
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/* FIXME check @offset, @width */
|
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@ -553,7 +549,7 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset,
|
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} else {
|
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value = extract32(value, 0, pfl->bank_width * 8);
|
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}
|
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DPRINTF("%s: block write of %x bytes\n", __func__, value);
|
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trace_pflash_write_block(pfl->name, value);
|
||||
pfl->counter = value;
|
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pfl->wcycle++;
|
||||
break;
|
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@ -567,7 +563,7 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset,
|
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} else if (cmd == 0xff) { /* Read Array */
|
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goto mode_read_array;
|
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} else {
|
||||
DPRINTF("%s: Unknown (un)locking command\n", __func__);
|
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trace_pflash_write(pfl->name, "unknown (un)locking command");
|
||||
goto mode_read_array;
|
||||
}
|
||||
break;
|
||||
@ -575,7 +571,7 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset,
|
||||
if (cmd == 0xff) { /* Read Array */
|
||||
goto mode_read_array;
|
||||
} else {
|
||||
DPRINTF("%s: leaving query mode\n", __func__);
|
||||
trace_pflash_write(pfl->name, "leaving query mode");
|
||||
}
|
||||
break;
|
||||
default:
|
||||
@ -603,7 +599,7 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset,
|
||||
hwaddr mask = pfl->writeblock_size - 1;
|
||||
mask = ~mask;
|
||||
|
||||
DPRINTF("%s: block write finished\n", __func__);
|
||||
trace_pflash_write(pfl->name, "block write finished");
|
||||
pfl->wcycle++;
|
||||
if (!pfl->ro) {
|
||||
/* Flush the entire write buffer onto backing storage. */
|
||||
@ -642,7 +638,7 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset,
|
||||
break;
|
||||
default:
|
||||
/* Should never happen */
|
||||
DPRINTF("%s: invalid write state\n", __func__);
|
||||
trace_pflash_write(pfl->name, "invalid write state");
|
||||
goto mode_read_array;
|
||||
}
|
||||
return;
|
||||
@ -653,7 +649,7 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset,
|
||||
"\n", __func__, offset, pfl->wcycle, pfl->cmd, value);
|
||||
|
||||
mode_read_array:
|
||||
trace_pflash_reset();
|
||||
trace_pflash_mode_read_array(pfl->name);
|
||||
memory_region_rom_device_set_romd(&pfl->mem, true);
|
||||
pfl->wcycle = 0;
|
||||
pfl->cmd = 0x00; /* This model reset value for READ_ARRAY (not CFI) */
|
||||
@ -694,31 +690,13 @@ static const MemoryRegionOps pflash_cfi01_ops = {
|
||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
||||
};
|
||||
|
||||
static void pflash_cfi01_realize(DeviceState *dev, Error **errp)
|
||||
static void pflash_cfi01_fill_cfi_table(PFlashCFI01 *pfl)
|
||||
{
|
||||
ERRP_GUARD();
|
||||
PFlashCFI01 *pfl = PFLASH_CFI01(dev);
|
||||
uint64_t total_len;
|
||||
int ret;
|
||||
uint64_t blocks_per_device, sector_len_per_device, device_len;
|
||||
int num_devices;
|
||||
|
||||
if (pfl->sector_len == 0) {
|
||||
error_setg(errp, "attribute \"sector-length\" not specified or zero.");
|
||||
return;
|
||||
}
|
||||
if (pfl->nb_blocs == 0) {
|
||||
error_setg(errp, "attribute \"num-blocks\" not specified or zero.");
|
||||
return;
|
||||
}
|
||||
if (pfl->name == NULL) {
|
||||
error_setg(errp, "attribute \"name\" not specified.");
|
||||
return;
|
||||
}
|
||||
|
||||
total_len = pfl->sector_len * pfl->nb_blocs;
|
||||
|
||||
/* These are only used to expose the parameters of each device
|
||||
/*
|
||||
* These are only used to expose the parameters of each device
|
||||
* in the cfi_table[].
|
||||
*/
|
||||
num_devices = pfl->device_width ? (pfl->bank_width / pfl->device_width) : 1;
|
||||
@ -731,52 +709,6 @@ static void pflash_cfi01_realize(DeviceState *dev, Error **errp)
|
||||
}
|
||||
device_len = sector_len_per_device * blocks_per_device;
|
||||
|
||||
memory_region_init_rom_device(
|
||||
&pfl->mem, OBJECT(dev),
|
||||
&pflash_cfi01_ops,
|
||||
pfl,
|
||||
pfl->name, total_len, errp);
|
||||
if (*errp) {
|
||||
return;
|
||||
}
|
||||
|
||||
pfl->storage = memory_region_get_ram_ptr(&pfl->mem);
|
||||
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem);
|
||||
|
||||
if (pfl->blk) {
|
||||
uint64_t perm;
|
||||
pfl->ro = !blk_supports_write_perm(pfl->blk);
|
||||
perm = BLK_PERM_CONSISTENT_READ | (pfl->ro ? 0 : BLK_PERM_WRITE);
|
||||
ret = blk_set_perm(pfl->blk, perm, BLK_PERM_ALL, errp);
|
||||
if (ret < 0) {
|
||||
return;
|
||||
}
|
||||
} else {
|
||||
pfl->ro = 0;
|
||||
}
|
||||
|
||||
if (pfl->blk) {
|
||||
if (!blk_check_size_and_read_all(pfl->blk, pfl->storage, total_len,
|
||||
errp)) {
|
||||
vmstate_unregister_ram(&pfl->mem, DEVICE(pfl));
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
/* Default to devices being used at their maximum device width. This was
|
||||
* assumed before the device_width support was added.
|
||||
*/
|
||||
if (!pfl->max_device_width) {
|
||||
pfl->max_device_width = pfl->device_width;
|
||||
}
|
||||
|
||||
pfl->wcycle = 0;
|
||||
/*
|
||||
* The command 0x00 is not assigned by the CFI open standard,
|
||||
* but QEMU historically uses it for the READ_ARRAY command (0xff).
|
||||
*/
|
||||
pfl->cmd = 0x00;
|
||||
pfl->status = 0x80; /* WSM ready */
|
||||
/* Hardcoded CFI table */
|
||||
/* Standard "QRY" string */
|
||||
pfl->cfi_table[0x10] = 'Q';
|
||||
@ -864,10 +796,83 @@ static void pflash_cfi01_realize(DeviceState *dev, Error **errp)
|
||||
pfl->cfi_table[0x3f] = 0x01; /* Number of protection fields */
|
||||
}
|
||||
|
||||
static void pflash_cfi01_realize(DeviceState *dev, Error **errp)
|
||||
{
|
||||
ERRP_GUARD();
|
||||
PFlashCFI01 *pfl = PFLASH_CFI01(dev);
|
||||
uint64_t total_len;
|
||||
int ret;
|
||||
|
||||
if (pfl->sector_len == 0) {
|
||||
error_setg(errp, "attribute \"sector-length\" not specified or zero.");
|
||||
return;
|
||||
}
|
||||
if (pfl->nb_blocs == 0) {
|
||||
error_setg(errp, "attribute \"num-blocks\" not specified or zero.");
|
||||
return;
|
||||
}
|
||||
if (pfl->name == NULL) {
|
||||
error_setg(errp, "attribute \"name\" not specified.");
|
||||
return;
|
||||
}
|
||||
|
||||
total_len = pfl->sector_len * pfl->nb_blocs;
|
||||
|
||||
memory_region_init_rom_device(
|
||||
&pfl->mem, OBJECT(dev),
|
||||
&pflash_cfi01_ops,
|
||||
pfl,
|
||||
pfl->name, total_len, errp);
|
||||
if (*errp) {
|
||||
return;
|
||||
}
|
||||
|
||||
pfl->storage = memory_region_get_ram_ptr(&pfl->mem);
|
||||
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem);
|
||||
|
||||
if (pfl->blk) {
|
||||
uint64_t perm;
|
||||
pfl->ro = !blk_supports_write_perm(pfl->blk);
|
||||
perm = BLK_PERM_CONSISTENT_READ | (pfl->ro ? 0 : BLK_PERM_WRITE);
|
||||
ret = blk_set_perm(pfl->blk, perm, BLK_PERM_ALL, errp);
|
||||
if (ret < 0) {
|
||||
return;
|
||||
}
|
||||
} else {
|
||||
pfl->ro = false;
|
||||
}
|
||||
|
||||
if (pfl->blk) {
|
||||
if (!blk_check_size_and_read_all(pfl->blk, pfl->storage, total_len,
|
||||
errp)) {
|
||||
vmstate_unregister_ram(&pfl->mem, DEVICE(pfl));
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Default to devices being used at their maximum device width. This was
|
||||
* assumed before the device_width support was added.
|
||||
*/
|
||||
if (!pfl->max_device_width) {
|
||||
pfl->max_device_width = pfl->device_width;
|
||||
}
|
||||
|
||||
pfl->wcycle = 0;
|
||||
/*
|
||||
* The command 0x00 is not assigned by the CFI open standard,
|
||||
* but QEMU historically uses it for the READ_ARRAY command (0xff).
|
||||
*/
|
||||
pfl->cmd = 0x00;
|
||||
pfl->status = 0x80; /* WSM ready */
|
||||
pflash_cfi01_fill_cfi_table(pfl);
|
||||
}
|
||||
|
||||
static void pflash_cfi01_system_reset(DeviceState *dev)
|
||||
{
|
||||
PFlashCFI01 *pfl = PFLASH_CFI01(dev);
|
||||
|
||||
trace_pflash_reset(pfl->name);
|
||||
/*
|
||||
* The command 0x00 is not assigned by the CFI open standard,
|
||||
* but QEMU historically uses it for the READ_ARRAY command (0xff).
|
||||
@ -1022,7 +1027,7 @@ static void postload_update_cb(void *opaque, bool running, RunState state)
|
||||
qemu_del_vm_change_state_handler(pfl->vmstate);
|
||||
pfl->vmstate = NULL;
|
||||
|
||||
DPRINTF("%s: updating bdrv for %s\n", __func__, pfl->name);
|
||||
trace_pflash_postload_cb(pfl->name);
|
||||
pflash_update(pfl, 0, pfl->sector_len * pfl->nb_blocs);
|
||||
}
|
||||
|
||||
|
||||
@ -48,14 +48,6 @@
|
||||
#include "migration/vmstate.h"
|
||||
#include "trace.h"
|
||||
|
||||
#define PFLASH_DEBUG false
|
||||
#define DPRINTF(fmt, ...) \
|
||||
do { \
|
||||
if (PFLASH_DEBUG) { \
|
||||
fprintf(stderr, "PFLASH: " fmt, ## __VA_ARGS__); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define PFLASH_LAZY_ROMD_THRESHOLD 42
|
||||
|
||||
/*
|
||||
@ -100,14 +92,15 @@ struct PFlashCFI02 {
|
||||
uint16_t unlock_addr1;
|
||||
uint8_t cfi_table[0x4d];
|
||||
QEMUTimer timer;
|
||||
/* The device replicates the flash memory across its memory space. Emulate
|
||||
/*
|
||||
* The device replicates the flash memory across its memory space. Emulate
|
||||
* that by having a container (.mem) filled with an array of aliases
|
||||
* (.mem_mappings) pointing to the flash memory (.orig_mem).
|
||||
*/
|
||||
MemoryRegion mem;
|
||||
MemoryRegion *mem_mappings; /* array; one per mapping */
|
||||
MemoryRegion orig_mem;
|
||||
int rom_mode;
|
||||
bool rom_mode;
|
||||
int read_counter; /* used for lazy switch-back to rom mode */
|
||||
int sectors_to_erase;
|
||||
uint64_t erase_time_remaining;
|
||||
@ -180,12 +173,22 @@ static void pflash_setup_mappings(PFlashCFI02 *pfl)
|
||||
"pflash-alias", &pfl->orig_mem, 0, size);
|
||||
memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]);
|
||||
}
|
||||
pfl->rom_mode = true;
|
||||
}
|
||||
|
||||
static void pflash_register_memory(PFlashCFI02 *pfl, int rom_mode)
|
||||
static void pflash_reset_state_machine(PFlashCFI02 *pfl)
|
||||
{
|
||||
memory_region_rom_device_set_romd(&pfl->orig_mem, rom_mode);
|
||||
pfl->rom_mode = rom_mode;
|
||||
trace_pflash_reset(pfl->name);
|
||||
pfl->cmd = 0x00;
|
||||
pfl->wcycle = 0;
|
||||
}
|
||||
|
||||
static void pflash_mode_read_array(PFlashCFI02 *pfl)
|
||||
{
|
||||
trace_pflash_mode_read_array(pfl->name);
|
||||
pflash_reset_state_machine(pfl);
|
||||
pfl->rom_mode = true;
|
||||
memory_region_rom_device_set_romd(&pfl->orig_mem, true);
|
||||
}
|
||||
|
||||
static size_t pflash_regions_count(PFlashCFI02 *pfl)
|
||||
@ -220,7 +223,7 @@ static void pflash_timer(void *opaque)
|
||||
{
|
||||
PFlashCFI02 *pfl = opaque;
|
||||
|
||||
trace_pflash_timer_expired(pfl->cmd);
|
||||
trace_pflash_timer_expired(pfl->name, pfl->cmd);
|
||||
if (pfl->cmd == 0x30) {
|
||||
/*
|
||||
* Sector erase. If DQ3 is 0 when the timer expires, then the 50
|
||||
@ -233,11 +236,10 @@ static void pflash_timer(void *opaque)
|
||||
uint64_t timeout = pflash_erase_time(pfl);
|
||||
timer_mod(&pfl->timer,
|
||||
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout);
|
||||
DPRINTF("%s: erase timeout fired; erasing %d sectors\n",
|
||||
__func__, pfl->sectors_to_erase);
|
||||
trace_pflash_erase_timeout(pfl->name, pfl->sectors_to_erase);
|
||||
return;
|
||||
}
|
||||
DPRINTF("%s: sector erase complete\n", __func__);
|
||||
trace_pflash_erase_complete(pfl->name);
|
||||
bitmap_zero(pfl->sector_erase_map, pfl->total_sectors);
|
||||
pfl->sectors_to_erase = 0;
|
||||
reset_dq3(pfl);
|
||||
@ -247,11 +249,10 @@ static void pflash_timer(void *opaque)
|
||||
toggle_dq7(pfl);
|
||||
if (pfl->bypass) {
|
||||
pfl->wcycle = 2;
|
||||
pfl->cmd = 0;
|
||||
} else {
|
||||
pflash_register_memory(pfl, 1);
|
||||
pfl->wcycle = 0;
|
||||
pflash_mode_read_array(pfl);
|
||||
}
|
||||
pfl->cmd = 0;
|
||||
}
|
||||
|
||||
/*
|
||||
@ -262,7 +263,7 @@ static uint64_t pflash_data_read(PFlashCFI02 *pfl, hwaddr offset,
|
||||
{
|
||||
uint8_t *p = (uint8_t *)pfl->storage + offset;
|
||||
uint64_t ret = pfl->be ? ldn_be_p(p, width) : ldn_le_p(p, width);
|
||||
trace_pflash_data_read(offset, width, ret);
|
||||
trace_pflash_data_read(pfl->name, offset, width, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -313,7 +314,7 @@ static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int width)
|
||||
/* Lazy reset to ROMD mode after a certain amount of read accesses */
|
||||
if (!pfl->rom_mode && pfl->wcycle == 0 &&
|
||||
++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) {
|
||||
pflash_register_memory(pfl, 1);
|
||||
pflash_mode_read_array(pfl);
|
||||
}
|
||||
offset &= pfl->chip_len - 1;
|
||||
boff = offset & 0xFF;
|
||||
@ -325,9 +326,8 @@ static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int width)
|
||||
switch (pfl->cmd) {
|
||||
default:
|
||||
/* This should never happen : reset state & treat it as a read*/
|
||||
DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
|
||||
pfl->wcycle = 0;
|
||||
pfl->cmd = 0;
|
||||
trace_pflash_read_unknown_state(pfl->name, pfl->cmd);
|
||||
pflash_reset_state_machine(pfl);
|
||||
/* fall through to the read code */
|
||||
case 0x80: /* Erase (unlock) */
|
||||
/* We accept reads during second unlock sequence... */
|
||||
@ -338,7 +338,7 @@ static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int width)
|
||||
toggle_dq2(pfl);
|
||||
/* Status register read */
|
||||
ret = pfl->status;
|
||||
DPRINTF("%s: status %" PRIx64 "\n", __func__, ret);
|
||||
trace_pflash_read_status(pfl->name, ret);
|
||||
break;
|
||||
}
|
||||
/* Flash area read */
|
||||
@ -363,7 +363,7 @@ static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int width)
|
||||
default:
|
||||
ret = pflash_data_read(pfl, offset, width);
|
||||
}
|
||||
DPRINTF("%s: ID " TARGET_FMT_plx " %" PRIx64 "\n", __func__, boff, ret);
|
||||
trace_pflash_read_done(pfl->name, boff, ret);
|
||||
break;
|
||||
case 0x10: /* Chip Erase */
|
||||
case 0x30: /* Sector Erase */
|
||||
@ -375,7 +375,7 @@ static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int width)
|
||||
toggle_dq6(pfl);
|
||||
/* Status register read */
|
||||
ret = pfl->status;
|
||||
DPRINTF("%s: status %" PRIx64 "\n", __func__, ret);
|
||||
trace_pflash_read_status(pfl->name, ret);
|
||||
break;
|
||||
case 0x98:
|
||||
/* CFI query mode */
|
||||
@ -386,7 +386,7 @@ static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int width)
|
||||
}
|
||||
break;
|
||||
}
|
||||
trace_pflash_io_read(offset, width, ret, pfl->cmd, pfl->wcycle);
|
||||
trace_pflash_io_read(pfl->name, offset, width, ret, pfl->cmd, pfl->wcycle);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -415,9 +415,8 @@ static void pflash_sector_erase(PFlashCFI02 *pfl, hwaddr offset)
|
||||
SectorInfo sector_info = pflash_sector_info(pfl, offset);
|
||||
uint64_t sector_len = sector_info.len;
|
||||
offset &= ~(sector_len - 1);
|
||||
DPRINTF("%s: start sector erase at %0*" PRIx64 "-%0*" PRIx64 "\n",
|
||||
__func__, pfl->width * 2, offset,
|
||||
pfl->width * 2, offset + sector_len - 1);
|
||||
trace_pflash_sector_erase_start(pfl->name, pfl->width * 2, offset,
|
||||
pfl->width * 2, offset + sector_len - 1);
|
||||
if (!pfl->ro) {
|
||||
uint8_t *p = pfl->storage;
|
||||
memset(p + offset, 0xff, sector_len);
|
||||
@ -438,7 +437,7 @@ static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
|
||||
uint8_t *p;
|
||||
uint8_t cmd;
|
||||
|
||||
trace_pflash_io_write(offset, width, value, pfl->wcycle);
|
||||
trace_pflash_io_write(pfl->name, offset, width, value, pfl->wcycle);
|
||||
cmd = value;
|
||||
if (pfl->cmd != 0xA0) {
|
||||
/* Reset does nothing during chip erase and sector erase. */
|
||||
@ -465,8 +464,10 @@ static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
|
||||
switch (pfl->wcycle) {
|
||||
case 0:
|
||||
/* Set the device in I/O access mode if required */
|
||||
if (pfl->rom_mode)
|
||||
pflash_register_memory(pfl, 0);
|
||||
if (pfl->rom_mode) {
|
||||
pfl->rom_mode = false;
|
||||
memory_region_rom_device_set_romd(&pfl->orig_mem, false);
|
||||
}
|
||||
pfl->read_counter = 0;
|
||||
/* We're in read mode */
|
||||
check_unlock0:
|
||||
@ -496,27 +497,25 @@ static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
|
||||
return;
|
||||
}
|
||||
if (boff != pfl->unlock_addr0 || cmd != 0xAA) {
|
||||
DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n",
|
||||
__func__, boff, cmd, pfl->unlock_addr0);
|
||||
trace_pflash_unlock0_failed(pfl->name, boff,
|
||||
cmd, pfl->unlock_addr0);
|
||||
goto reset_flash;
|
||||
}
|
||||
DPRINTF("%s: unlock sequence started\n", __func__);
|
||||
trace_pflash_write(pfl->name, "unlock sequence started");
|
||||
break;
|
||||
case 1:
|
||||
/* We started an unlock sequence */
|
||||
check_unlock1:
|
||||
if (boff != pfl->unlock_addr1 || cmd != 0x55) {
|
||||
DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__,
|
||||
boff, cmd);
|
||||
trace_pflash_unlock1_failed(pfl->name, boff, cmd);
|
||||
goto reset_flash;
|
||||
}
|
||||
DPRINTF("%s: unlock sequence done\n", __func__);
|
||||
trace_pflash_write(pfl->name, "unlock sequence done");
|
||||
break;
|
||||
case 2:
|
||||
/* We finished an unlock sequence */
|
||||
if (!pfl->bypass && boff != pfl->unlock_addr0) {
|
||||
DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__,
|
||||
boff, cmd);
|
||||
trace_pflash_write_failed(pfl->name, boff, cmd);
|
||||
goto reset_flash;
|
||||
}
|
||||
switch (cmd) {
|
||||
@ -527,10 +526,10 @@ static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
|
||||
case 0x90: /* Autoselect */
|
||||
case 0xA0: /* Program */
|
||||
pfl->cmd = cmd;
|
||||
DPRINTF("%s: starting command %02x\n", __func__, cmd);
|
||||
trace_pflash_write_start(pfl->name, cmd);
|
||||
break;
|
||||
default:
|
||||
DPRINTF("%s: unknown command %02x\n", __func__, cmd);
|
||||
trace_pflash_write_unknown(pfl->name, cmd);
|
||||
goto reset_flash;
|
||||
}
|
||||
break;
|
||||
@ -548,7 +547,7 @@ static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
|
||||
}
|
||||
goto reset_flash;
|
||||
}
|
||||
trace_pflash_data_write(offset, width, value, 0);
|
||||
trace_pflash_data_write(pfl->name, offset, width, value, 0);
|
||||
if (!pfl->ro) {
|
||||
p = (uint8_t *)pfl->storage + offset;
|
||||
if (pfl->be) {
|
||||
@ -586,8 +585,7 @@ static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
|
||||
}
|
||||
/* fall through */
|
||||
default:
|
||||
DPRINTF("%s: invalid write for command %02x\n",
|
||||
__func__, pfl->cmd);
|
||||
trace_pflash_write_invalid(pfl->name, pfl->cmd);
|
||||
goto reset_flash;
|
||||
}
|
||||
case 4:
|
||||
@ -600,8 +598,7 @@ static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
|
||||
goto check_unlock1;
|
||||
default:
|
||||
/* Should never happen */
|
||||
DPRINTF("%s: invalid command state %02x (wc 4)\n",
|
||||
__func__, pfl->cmd);
|
||||
trace_pflash_write_invalid_state(pfl->name, pfl->cmd, 5);
|
||||
goto reset_flash;
|
||||
}
|
||||
break;
|
||||
@ -613,12 +610,11 @@ static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
|
||||
switch (cmd) {
|
||||
case 0x10: /* Chip Erase */
|
||||
if (boff != pfl->unlock_addr0) {
|
||||
DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n",
|
||||
__func__, offset);
|
||||
trace_pflash_chip_erase_invalid(pfl->name, offset);
|
||||
goto reset_flash;
|
||||
}
|
||||
/* Chip erase */
|
||||
DPRINTF("%s: start chip erase\n", __func__);
|
||||
trace_pflash_chip_erase_start(pfl->name);
|
||||
if (!pfl->ro) {
|
||||
memset(pfl->storage, 0xff, pfl->chip_len);
|
||||
pflash_update(pfl, 0, pfl->chip_len);
|
||||
@ -632,7 +628,7 @@ static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
|
||||
pflash_sector_erase(pfl, offset);
|
||||
break;
|
||||
default:
|
||||
DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
|
||||
trace_pflash_write_invalid_command(pfl->name, cmd);
|
||||
goto reset_flash;
|
||||
}
|
||||
pfl->cmd = cmd;
|
||||
@ -663,8 +659,7 @@ static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
|
||||
}
|
||||
reset_dq3(pfl);
|
||||
timer_del(&pfl->timer);
|
||||
pfl->wcycle = 0;
|
||||
pfl->cmd = 0;
|
||||
pflash_reset_state_machine(pfl);
|
||||
return;
|
||||
}
|
||||
/*
|
||||
@ -683,19 +678,18 @@ static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
|
||||
return;
|
||||
default:
|
||||
/* Should never happen */
|
||||
DPRINTF("%s: invalid command state %02x (wc 6)\n",
|
||||
__func__, pfl->cmd);
|
||||
trace_pflash_write_invalid_state(pfl->name, pfl->cmd, 6);
|
||||
goto reset_flash;
|
||||
}
|
||||
break;
|
||||
/* Special values for CFI queries */
|
||||
case WCYCLE_CFI:
|
||||
case WCYCLE_AUTOSELECT_CFI:
|
||||
DPRINTF("%s: invalid write in CFI query mode\n", __func__);
|
||||
trace_pflash_write(pfl->name, "invalid write in CFI query mode");
|
||||
goto reset_flash;
|
||||
default:
|
||||
/* Should never happen */
|
||||
DPRINTF("%s: invalid write state (wc 7)\n", __func__);
|
||||
trace_pflash_write(pfl->name, "invalid write state (wc 7)");
|
||||
goto reset_flash;
|
||||
}
|
||||
pfl->wcycle++;
|
||||
@ -704,10 +698,8 @@ static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
|
||||
|
||||
/* Reset flash */
|
||||
reset_flash:
|
||||
trace_pflash_reset();
|
||||
pfl->bypass = 0;
|
||||
pfl->wcycle = 0;
|
||||
pfl->cmd = 0;
|
||||
pflash_reset_state_machine(pfl);
|
||||
return;
|
||||
|
||||
do_bypass:
|
||||
@ -723,6 +715,104 @@ static const MemoryRegionOps pflash_cfi02_ops = {
|
||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
||||
};
|
||||
|
||||
static void pflash_cfi02_fill_cfi_table(PFlashCFI02 *pfl, int nb_regions)
|
||||
{
|
||||
/* Hardcoded CFI table (mostly from SG29 Spansion flash) */
|
||||
const uint16_t pri_ofs = 0x40;
|
||||
/* Standard "QRY" string */
|
||||
pfl->cfi_table[0x10] = 'Q';
|
||||
pfl->cfi_table[0x11] = 'R';
|
||||
pfl->cfi_table[0x12] = 'Y';
|
||||
/* Command set (AMD/Fujitsu) */
|
||||
pfl->cfi_table[0x13] = 0x02;
|
||||
pfl->cfi_table[0x14] = 0x00;
|
||||
/* Primary extended table address */
|
||||
pfl->cfi_table[0x15] = pri_ofs;
|
||||
pfl->cfi_table[0x16] = pri_ofs >> 8;
|
||||
/* Alternate command set (none) */
|
||||
pfl->cfi_table[0x17] = 0x00;
|
||||
pfl->cfi_table[0x18] = 0x00;
|
||||
/* Alternate extended table (none) */
|
||||
pfl->cfi_table[0x19] = 0x00;
|
||||
pfl->cfi_table[0x1A] = 0x00;
|
||||
/* Vcc min */
|
||||
pfl->cfi_table[0x1B] = 0x27;
|
||||
/* Vcc max */
|
||||
pfl->cfi_table[0x1C] = 0x36;
|
||||
/* Vpp min (no Vpp pin) */
|
||||
pfl->cfi_table[0x1D] = 0x00;
|
||||
/* Vpp max (no Vpp pin) */
|
||||
pfl->cfi_table[0x1E] = 0x00;
|
||||
/* Timeout per single byte/word write (128 ms) */
|
||||
pfl->cfi_table[0x1F] = 0x07;
|
||||
/* Timeout for min size buffer write (NA) */
|
||||
pfl->cfi_table[0x20] = 0x00;
|
||||
/* Typical timeout for block erase (512 ms) */
|
||||
pfl->cfi_table[0x21] = 0x09;
|
||||
/* Typical timeout for full chip erase (4096 ms) */
|
||||
pfl->cfi_table[0x22] = 0x0C;
|
||||
/* Reserved */
|
||||
pfl->cfi_table[0x23] = 0x01;
|
||||
/* Max timeout for buffer write (NA) */
|
||||
pfl->cfi_table[0x24] = 0x00;
|
||||
/* Max timeout for block erase */
|
||||
pfl->cfi_table[0x25] = 0x0A;
|
||||
/* Max timeout for chip erase */
|
||||
pfl->cfi_table[0x26] = 0x0D;
|
||||
/* Device size */
|
||||
pfl->cfi_table[0x27] = ctz32(pfl->chip_len);
|
||||
/* Flash device interface (8 & 16 bits) */
|
||||
pfl->cfi_table[0x28] = 0x02;
|
||||
pfl->cfi_table[0x29] = 0x00;
|
||||
/* Max number of bytes in multi-bytes write */
|
||||
/*
|
||||
* XXX: disable buffered write as it's not supported
|
||||
* pfl->cfi_table[0x2A] = 0x05;
|
||||
*/
|
||||
pfl->cfi_table[0x2A] = 0x00;
|
||||
pfl->cfi_table[0x2B] = 0x00;
|
||||
/* Number of erase block regions */
|
||||
pfl->cfi_table[0x2c] = nb_regions;
|
||||
/* Erase block regions */
|
||||
for (int i = 0; i < nb_regions; ++i) {
|
||||
uint32_t sector_len_per_device = pfl->sector_len[i];
|
||||
pfl->cfi_table[0x2d + 4 * i] = pfl->nb_blocs[i] - 1;
|
||||
pfl->cfi_table[0x2e + 4 * i] = (pfl->nb_blocs[i] - 1) >> 8;
|
||||
pfl->cfi_table[0x2f + 4 * i] = sector_len_per_device >> 8;
|
||||
pfl->cfi_table[0x30 + 4 * i] = sector_len_per_device >> 16;
|
||||
}
|
||||
assert(0x2c + 4 * nb_regions < pri_ofs);
|
||||
|
||||
/* Extended */
|
||||
pfl->cfi_table[0x00 + pri_ofs] = 'P';
|
||||
pfl->cfi_table[0x01 + pri_ofs] = 'R';
|
||||
pfl->cfi_table[0x02 + pri_ofs] = 'I';
|
||||
|
||||
/* Extended version 1.0 */
|
||||
pfl->cfi_table[0x03 + pri_ofs] = '1';
|
||||
pfl->cfi_table[0x04 + pri_ofs] = '0';
|
||||
|
||||
/* Address sensitive unlock required. */
|
||||
pfl->cfi_table[0x05 + pri_ofs] = 0x00;
|
||||
/* Erase suspend to read/write. */
|
||||
pfl->cfi_table[0x06 + pri_ofs] = 0x02;
|
||||
/* Sector protect not supported. */
|
||||
pfl->cfi_table[0x07 + pri_ofs] = 0x00;
|
||||
/* Temporary sector unprotect not supported. */
|
||||
pfl->cfi_table[0x08 + pri_ofs] = 0x00;
|
||||
|
||||
/* Sector protect/unprotect scheme. */
|
||||
pfl->cfi_table[0x09 + pri_ofs] = 0x00;
|
||||
|
||||
/* Simultaneous operation not supported. */
|
||||
pfl->cfi_table[0x0a + pri_ofs] = 0x00;
|
||||
/* Burst mode not supported. */
|
||||
pfl->cfi_table[0x0b + pri_ofs] = 0x00;
|
||||
/* Page mode not supported. */
|
||||
pfl->cfi_table[0x0c + pri_ofs] = 0x00;
|
||||
assert(0x0c + pri_ofs < ARRAY_SIZE(pfl->cfi_table));
|
||||
}
|
||||
|
||||
static void pflash_cfi02_realize(DeviceState *dev, Error **errp)
|
||||
{
|
||||
ERRP_GUARD();
|
||||
@ -828,106 +918,19 @@ static void pflash_cfi02_realize(DeviceState *dev, Error **errp)
|
||||
pfl->sector_erase_map = bitmap_new(pfl->total_sectors);
|
||||
|
||||
pflash_setup_mappings(pfl);
|
||||
pfl->rom_mode = 1;
|
||||
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem);
|
||||
|
||||
timer_init_ns(&pfl->timer, QEMU_CLOCK_VIRTUAL, pflash_timer, pfl);
|
||||
pfl->wcycle = 0;
|
||||
pfl->cmd = 0;
|
||||
pfl->status = 0;
|
||||
|
||||
/* Hardcoded CFI table (mostly from SG29 Spansion flash) */
|
||||
const uint16_t pri_ofs = 0x40;
|
||||
/* Standard "QRY" string */
|
||||
pfl->cfi_table[0x10] = 'Q';
|
||||
pfl->cfi_table[0x11] = 'R';
|
||||
pfl->cfi_table[0x12] = 'Y';
|
||||
/* Command set (AMD/Fujitsu) */
|
||||
pfl->cfi_table[0x13] = 0x02;
|
||||
pfl->cfi_table[0x14] = 0x00;
|
||||
/* Primary extended table address */
|
||||
pfl->cfi_table[0x15] = pri_ofs;
|
||||
pfl->cfi_table[0x16] = pri_ofs >> 8;
|
||||
/* Alternate command set (none) */
|
||||
pfl->cfi_table[0x17] = 0x00;
|
||||
pfl->cfi_table[0x18] = 0x00;
|
||||
/* Alternate extended table (none) */
|
||||
pfl->cfi_table[0x19] = 0x00;
|
||||
pfl->cfi_table[0x1A] = 0x00;
|
||||
/* Vcc min */
|
||||
pfl->cfi_table[0x1B] = 0x27;
|
||||
/* Vcc max */
|
||||
pfl->cfi_table[0x1C] = 0x36;
|
||||
/* Vpp min (no Vpp pin) */
|
||||
pfl->cfi_table[0x1D] = 0x00;
|
||||
/* Vpp max (no Vpp pin) */
|
||||
pfl->cfi_table[0x1E] = 0x00;
|
||||
/* Timeout per single byte/word write (128 ms) */
|
||||
pfl->cfi_table[0x1F] = 0x07;
|
||||
/* Timeout for min size buffer write (NA) */
|
||||
pfl->cfi_table[0x20] = 0x00;
|
||||
/* Typical timeout for block erase (512 ms) */
|
||||
pfl->cfi_table[0x21] = 0x09;
|
||||
/* Typical timeout for full chip erase (4096 ms) */
|
||||
pfl->cfi_table[0x22] = 0x0C;
|
||||
/* Reserved */
|
||||
pfl->cfi_table[0x23] = 0x01;
|
||||
/* Max timeout for buffer write (NA) */
|
||||
pfl->cfi_table[0x24] = 0x00;
|
||||
/* Max timeout for block erase */
|
||||
pfl->cfi_table[0x25] = 0x0A;
|
||||
/* Max timeout for chip erase */
|
||||
pfl->cfi_table[0x26] = 0x0D;
|
||||
/* Device size */
|
||||
pfl->cfi_table[0x27] = ctz32(pfl->chip_len);
|
||||
/* Flash device interface (8 & 16 bits) */
|
||||
pfl->cfi_table[0x28] = 0x02;
|
||||
pfl->cfi_table[0x29] = 0x00;
|
||||
/* Max number of bytes in multi-bytes write */
|
||||
/* XXX: disable buffered write as it's not supported */
|
||||
// pfl->cfi_table[0x2A] = 0x05;
|
||||
pfl->cfi_table[0x2A] = 0x00;
|
||||
pfl->cfi_table[0x2B] = 0x00;
|
||||
/* Number of erase block regions */
|
||||
pfl->cfi_table[0x2c] = nb_regions;
|
||||
/* Erase block regions */
|
||||
for (int i = 0; i < nb_regions; ++i) {
|
||||
uint32_t sector_len_per_device = pfl->sector_len[i];
|
||||
pfl->cfi_table[0x2d + 4 * i] = pfl->nb_blocs[i] - 1;
|
||||
pfl->cfi_table[0x2e + 4 * i] = (pfl->nb_blocs[i] - 1) >> 8;
|
||||
pfl->cfi_table[0x2f + 4 * i] = sector_len_per_device >> 8;
|
||||
pfl->cfi_table[0x30 + 4 * i] = sector_len_per_device >> 16;
|
||||
}
|
||||
assert(0x2c + 4 * nb_regions < pri_ofs);
|
||||
pflash_cfi02_fill_cfi_table(pfl, nb_regions);
|
||||
}
|
||||
|
||||
/* Extended */
|
||||
pfl->cfi_table[0x00 + pri_ofs] = 'P';
|
||||
pfl->cfi_table[0x01 + pri_ofs] = 'R';
|
||||
pfl->cfi_table[0x02 + pri_ofs] = 'I';
|
||||
static void pflash_cfi02_reset(DeviceState *dev)
|
||||
{
|
||||
PFlashCFI02 *pfl = PFLASH_CFI02(dev);
|
||||
|
||||
/* Extended version 1.0 */
|
||||
pfl->cfi_table[0x03 + pri_ofs] = '1';
|
||||
pfl->cfi_table[0x04 + pri_ofs] = '0';
|
||||
|
||||
/* Address sensitive unlock required. */
|
||||
pfl->cfi_table[0x05 + pri_ofs] = 0x00;
|
||||
/* Erase suspend to read/write. */
|
||||
pfl->cfi_table[0x06 + pri_ofs] = 0x02;
|
||||
/* Sector protect not supported. */
|
||||
pfl->cfi_table[0x07 + pri_ofs] = 0x00;
|
||||
/* Temporary sector unprotect not supported. */
|
||||
pfl->cfi_table[0x08 + pri_ofs] = 0x00;
|
||||
|
||||
/* Sector protect/unprotect scheme. */
|
||||
pfl->cfi_table[0x09 + pri_ofs] = 0x00;
|
||||
|
||||
/* Simultaneous operation not supported. */
|
||||
pfl->cfi_table[0x0a + pri_ofs] = 0x00;
|
||||
/* Burst mode not supported. */
|
||||
pfl->cfi_table[0x0b + pri_ofs] = 0x00;
|
||||
/* Page mode not supported. */
|
||||
pfl->cfi_table[0x0c + pri_ofs] = 0x00;
|
||||
assert(0x0c + pri_ofs < ARRAY_SIZE(pfl->cfi_table));
|
||||
pflash_reset_state_machine(pfl);
|
||||
}
|
||||
|
||||
static Property pflash_cfi02_properties[] = {
|
||||
@ -967,6 +970,7 @@ static void pflash_cfi02_class_init(ObjectClass *klass, void *data)
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
|
||||
dc->realize = pflash_cfi02_realize;
|
||||
dc->reset = pflash_cfi02_reset;
|
||||
dc->unrealize = pflash_cfi02_unrealize;
|
||||
device_class_set_props(dc, pflash_cfi02_properties);
|
||||
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
|
||||
|
||||
@ -6,15 +6,37 @@ fdc_ioport_write(uint8_t reg, uint8_t value) "write reg 0x%02x val 0x%02x"
|
||||
|
||||
# pflash_cfi01.c
|
||||
# pflash_cfi02.c
|
||||
pflash_reset(void) "reset"
|
||||
pflash_timer_expired(uint8_t cmd) "command 0x%02x done"
|
||||
pflash_io_read(uint64_t offset, unsigned size, uint32_t value, uint8_t cmd, uint8_t wcycle) "offset:0x%04"PRIx64" size:%u value:0x%04x cmd:0x%02x wcycle:%u"
|
||||
pflash_io_write(uint64_t offset, unsigned size, uint32_t value, uint8_t wcycle) "offset:0x%04"PRIx64" size:%u value:0x%04x wcycle:%u"
|
||||
pflash_data_read(uint64_t offset, unsigned size, uint32_t value) "data offset:0x%04"PRIx64" size:%u value:0x%04x"
|
||||
pflash_data_write(uint64_t offset, unsigned size, uint32_t value, uint64_t counter) "data offset:0x%04"PRIx64" size:%u value:0x%04x counter:0x%016"PRIx64
|
||||
pflash_manufacturer_id(uint16_t id) "Read Manufacturer ID: 0x%04x"
|
||||
pflash_device_id(uint16_t id) "Read Device ID: 0x%04x"
|
||||
pflash_device_info(uint64_t offset) "Read Device Information offset:0x%04"PRIx64
|
||||
pflash_chip_erase_invalid(const char *name, uint64_t offset) "%s: chip erase: invalid address 0x%" PRIx64
|
||||
pflash_chip_erase_start(const char *name) "%s: start chip erase"
|
||||
pflash_data_read(const char *name, uint64_t offset, unsigned size, uint32_t value) "%s: data offset:0x%04"PRIx64" size:%u value:0x%04x"
|
||||
pflash_data_write(const char *name, uint64_t offset, unsigned size, uint32_t value, uint64_t counter) "%s: data offset:0x%04"PRIx64" size:%u value:0x%04x counter:0x%016"PRIx64
|
||||
pflash_device_id(const char *name, uint16_t id) "%s: read device ID: 0x%04x"
|
||||
pflash_device_info(const char *name, uint64_t offset) "%s: read device information offset:0x%04" PRIx64
|
||||
pflash_erase_complete(const char *name) "%s: sector erase complete"
|
||||
pflash_erase_timeout(const char *name, int count) "%s: erase timeout fired; erasing %d sectors"
|
||||
pflash_io_read(const char *name, uint64_t offset, unsigned int size, uint32_t value, uint8_t cmd, uint8_t wcycle) "%s: offset:0x%04" PRIx64 " size:%u value:0x%04x cmd:0x%02x wcycle:%u"
|
||||
pflash_io_write(const char *name, uint64_t offset, unsigned int size, uint32_t value, uint8_t wcycle) "%s: offset:0x%04"PRIx64" size:%u value:0x%04x wcycle:%u"
|
||||
pflash_manufacturer_id(const char *name, uint16_t id) "%s: read manufacturer ID: 0x%04x"
|
||||
pflash_mode_read_array(const char *name) "%s: read array mode"
|
||||
pflash_postload_cb(const char *name) "%s: updating bdrv"
|
||||
pflash_read_done(const char *name, uint64_t offset, uint64_t ret) "%s: ID:0x%" PRIx64 " ret:0x%" PRIx64
|
||||
pflash_read_status(const char *name, uint32_t ret) "%s: status:0x%x"
|
||||
pflash_read_unknown_state(const char *name, uint8_t cmd) "%s: unknown command state:0x%x"
|
||||
pflash_reset(const char *name) "%s: reset"
|
||||
pflash_sector_erase_start(const char *name, int width1, uint64_t start, int width2, uint64_t end) "%s: start sector erase at: 0x%0*" PRIx64 "-0x%0*" PRIx64
|
||||
pflash_timer_expired(const char *name, uint8_t cmd) "%s: command 0x%02x done"
|
||||
pflash_unlock0_failed(const char *name, uint64_t offset, uint8_t cmd, uint16_t addr0) "%s: unlock0 failed 0x%" PRIx64 " 0x%02x 0x%04x"
|
||||
pflash_unlock1_failed(const char *name, uint64_t offset, uint8_t cmd) "%s: unlock0 failed 0x%" PRIx64 " 0x%02x"
|
||||
pflash_unsupported_device_configuration(const char *name, uint8_t width, uint8_t max) "%s: unsupported device configuration: device_width:%d max_device_width:%d"
|
||||
pflash_write(const char *name, const char *str) "%s: %s"
|
||||
pflash_write_block(const char *name, uint32_t value) "%s: block write: bytes:0x%x"
|
||||
pflash_write_block_erase(const char *name, uint64_t offset, uint64_t len) "%s: block erase offset:0x%" PRIx64 " bytes:0x%" PRIx64
|
||||
pflash_write_failed(const char *name, uint64_t offset, uint8_t cmd) "%s: command failed 0x%" PRIx64 " 0x%02x"
|
||||
pflash_write_invalid(const char *name, uint8_t cmd) "%s: invalid write for command 0x%02x"
|
||||
pflash_write_invalid_command(const char *name, uint8_t cmd) "%s: invalid command 0x%02x (wc 5)"
|
||||
pflash_write_invalid_state(const char *name, uint8_t cmd, int wc) "%s: invalid command state 0x%02x (wc %d)"
|
||||
pflash_write_start(const char *name, uint8_t cmd) "%s: starting command 0x%02x"
|
||||
pflash_write_unknown(const char *name, uint8_t cmd) "%s: unknown command 0x%02x"
|
||||
|
||||
# virtio-blk.c
|
||||
virtio_blk_req_complete(void *vdev, void *req, int status) "vdev %p req %p status %d"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user