mirrors/qemu
0
0
Fork 0
mirror of https://github.com/qemu/qemu.git synced 2024-11-25 03:43:37 +08:00
Code Issues Packages Projects Releases Wiki Activity

linux-user/elfload: Implement ELF_HWCAP for RISC-V

Browse Source 
Set I, M, A, F, D and C bit for hwcap if misa is set.

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210706035015.122899-1-kito.cheng@sifive.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
This commit is contained in:
Kito Cheng 2021-07-06 11:50:15 +08:00 committed by Laurent Vivier
parent 9aef095419
commit cb46938c45
1 changed files with 13 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
linux-user/elfload.c
View File

@ -1434,6 +1434,19 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs,
#define ELF_CLASS ELFCLASS64
#endif
#define ELF_HWCAP get_elf_hwcap()
static uint32_t get_elf_hwcap(void)
{
#define MISA_BIT(EXT) (1 << (EXT - 'A'))
RISCVCPU *cpu = RISCV_CPU(thread_cpu);
uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A')
| MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C');
return cpu->env.misa & mask;
#undef MISA_BIT
}
static inline void init_thread(struct target_pt_regs *regs,
struct image_info *infop)
{