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target/mips: fix msa copy_[s|u]_df rd = 0 corner case

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This patch fixes the msa copy_[s|u]_df instruction emulation when
the destination register rd is zero. Without this patch the zero
register would get clobbered, which should never happen because it
is supposed to be hardwired to 0.

Fix this corner case by explicitly checking rd = 0 and effectively
making these instructions emulation no-op in that case.

Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
This commit is contained in:
Miodrag Dinic 2017-06-15 16:20:33 +02:00 committed by Yongbok Kim
parent b5ed2e11ef
commit cab4888136
1 changed files with 6 additions and 2 deletions
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8
target/mips/translate.c
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@ -18712,10 +18712,14 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
#endif
switch (MASK_MSA_ELM(ctx->opcode)) {
case OPC_COPY_S_df:
gen_helper_msa_copy_s_df(cpu_env, tdf, twd, tws, tn);
if (likely(wd != 0)) {
gen_helper_msa_copy_s_df(cpu_env, tdf, twd, tws, tn);
}
break;
case OPC_COPY_U_df:
gen_helper_msa_copy_u_df(cpu_env, tdf, twd, tws, tn);
if (likely(wd != 0)) {
gen_helper_msa_copy_u_df(cpu_env, tdf, twd, tws, tn);
}
break;
case OPC_INSERT_df:
gen_helper_msa_insert_df(cpu_env, tdf, twd, tws, tn);