mirror of
https://github.com/qemu/qemu.git
synced 2024-11-28 22:33:36 +08:00
Made the etrax timers and serial-ports base address relocatable. Use target_phys_addr_t instead of target_ulong.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4058 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
edgar_igl
parent
05ba7d5f34
commit
ca87d03b77
18
hw/etraxfs.c
18
hw/etraxfs.c
@ -35,10 +35,10 @@ static void main_cpu_reset(void *opaque)
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}
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/* Init functions for different blocks. */
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extern qemu_irq *etraxfs_pic_init(CPUState *env, target_ulong base);
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/* TODO: Make these blocks relocate:able. */
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extern void etraxfs_timer_init(CPUState *env, qemu_irq *irqs);
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extern void etraxfs_ser_init(CPUState *env, qemu_irq *irqs);
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extern qemu_irq *etraxfs_pic_init(CPUState *env, target_phys_addr_t base);
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void etraxfs_timer_init(CPUState *env, qemu_irq *irqs,
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target_phys_addr_t base);
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void etraxfs_ser_init(CPUState *env, qemu_irq *irqs, target_phys_addr_t base);
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static
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void bareetraxfs_init (int ram_size, int vga_ram_size,
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@ -84,8 +84,14 @@ void bareetraxfs_init (int ram_size, int vga_ram_size,
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4, 0x0000, 0x0000, 0x0000, 0x0000);
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pic = etraxfs_pic_init(env, 0xb001c000);
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etraxfs_timer_init(env, pic);
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etraxfs_ser_init(env, pic);
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/* 2 timers. */
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etraxfs_timer_init(env, pic, 0xb001e000);
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etraxfs_timer_init(env, pic, 0xb005e000);
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/* 4 serial ports. */
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etraxfs_ser_init(env, pic, 0xb0026000);
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etraxfs_ser_init(env, pic, 0xb0028000);
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etraxfs_ser_init(env, pic, 0xb002a000);
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etraxfs_ser_init(env, pic, 0xb002c000);
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kernel_size = load_image(kernel_filename, phys_ram_base + 0x4000);
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/* magic for boot. */
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@ -30,7 +30,7 @@
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struct fs_pic_state_t
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{
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CPUState *env;
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target_ulong base;
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target_phys_addr_t base;
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uint32_t rw_mask;
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/* Active interrupt lines. */
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@ -186,7 +186,7 @@ static void etraxfs_pic_handler(void *opaque, int irq, int level)
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}
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}
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qemu_irq *etraxfs_pic_init(CPUState *env, target_ulong base)
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qemu_irq *etraxfs_pic_init(CPUState *env, target_phys_addr_t base)
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{
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struct fs_pic_state_t *fs;
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qemu_irq *pic;
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@ -35,25 +35,20 @@
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static uint32_t ser_readb (void *opaque, target_phys_addr_t addr)
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{
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CPUState *env;
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uint32_t r = 0;
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env = opaque;
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D(CPUState *env = opaque);
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D(printf ("%s %x pc=%x\n", __func__, addr, env->pc));
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return r;
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return 0;
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}
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static uint32_t ser_readw (void *opaque, target_phys_addr_t addr)
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{
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CPUState *env;
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uint32_t r = 0;
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env = opaque;
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D(CPUState *env = opaque);
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D(printf ("%s %x pc=%x\n", __func__, addr, env->pc));
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return r;
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return 0;
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}
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static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
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{
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CPUState *env = opaque;
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D(CPUState *env = opaque);
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uint32_t r = 0;
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switch (addr & 0xfff)
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@ -75,21 +70,19 @@ static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
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static void
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ser_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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CPUState *env;
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env = opaque;
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D(CPUState *env = opaque);
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D(printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc));
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}
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static void
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ser_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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CPUState *env;
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env = opaque;
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D(CPUState *env = opaque);
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D(printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc));
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}
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static void
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ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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CPUState *env = opaque;
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D(CPUState *env = opaque);
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switch (addr & 0xfff)
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{
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@ -121,13 +114,9 @@ static CPUWriteMemoryFunc *ser_write[] = {
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&ser_writel,
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};
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void etraxfs_ser_init(CPUState *env, qemu_irq *irqs)
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void etraxfs_ser_init(CPUState *env, qemu_irq *irqs, target_phys_addr_t base)
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{
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int ser_regs;
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ser_regs = cpu_register_io_memory(0, ser_read, ser_write, env);
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cpu_register_physical_memory (0xb0026000, 0x3c, ser_regs);
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cpu_register_physical_memory (0xb0028000, 0x3c, ser_regs);
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cpu_register_physical_memory (0xb002a000, 0x3c, ser_regs);
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cpu_register_physical_memory (0xb002c000, 0x3c, ser_regs);
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cpu_register_physical_memory (base, 0x3c, ser_regs);
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}
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@ -28,27 +28,28 @@
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#define D(x)
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#define R_TIME 0xb001e038
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#define RW_TMR0_DIV 0xb001e000
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#define R_TMR0_DATA 0xb001e004
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#define RW_TMR0_CTRL 0xb001e008
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#define RW_TMR1_DIV 0xb001e010
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#define R_TMR1_DATA 0xb001e014
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#define RW_TMR1_CTRL 0xb001e018
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#define RW_WD_CTRL 0xb001e040
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#define RW_INTR_MASK 0xb001e048
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#define RW_ACK_INTR 0xb001e04c
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#define R_INTR 0xb001e050
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#define R_MASKED_INTR 0xb001e054
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#define RW_TMR0_DIV 0x00
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#define R_TMR0_DATA 0x04
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#define RW_TMR0_CTRL 0x08
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#define RW_TMR1_DIV 0x10
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#define R_TMR1_DATA 0x14
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#define RW_TMR1_CTRL 0x18
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#define R_TIME 0x38
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#define RW_WD_CTRL 0x40
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#define RW_INTR_MASK 0x48
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#define RW_ACK_INTR 0x4c
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#define R_INTR 0x50
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#define R_MASKED_INTR 0x54
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struct fs_timer_t {
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QEMUBH *bh;
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unsigned int limit;
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int scale;
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ptimer_state *ptimer;
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CPUState *env;
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qemu_irq *irq;
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target_phys_addr_t base;
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QEMUBH *bh;
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ptimer_state *ptimer;
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unsigned int limit;
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int scale;
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uint32_t mask;
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struct timeval last;
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@ -57,16 +58,6 @@ struct fs_timer_t {
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uint32_t r_intr;
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};
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static struct fs_timer_t timer[2];
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static inline int timer_index(target_phys_addr_t addr)
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{
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int t = 0;
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if (addr >= 0xb005e000)
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t = 1;
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return t;
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}
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/* diff two timevals. Return a single int in us. */
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int diff_timeval_us(struct timeval *a, struct timeval *b)
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{
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@ -78,31 +69,23 @@ int diff_timeval_us(struct timeval *a, struct timeval *b)
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return diff;
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}
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static uint32_t timer_readb (void *opaque, target_phys_addr_t addr)
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static uint32_t timer_rinvalid (void *opaque, target_phys_addr_t addr)
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{
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CPUState *env;
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uint32_t r = 0;
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env = opaque;
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D(printf ("%s %x pc=%x\n", __func__, addr, env->pc));
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return r;
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}
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static uint32_t timer_readw (void *opaque, target_phys_addr_t addr)
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{
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CPUState *env;
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uint32_t r = 0;
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env = opaque;
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D(printf ("%s %x pc=%x\n", __func__, addr, env->pc));
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return r;
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struct fs_timer_t *t = opaque;
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CPUState *env = t->env;
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cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
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addr, env->pc);
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return 0;
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}
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static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
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{
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CPUState *env = opaque;
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struct fs_timer_t *t = opaque;
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D(CPUState *env = t->env);
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uint32_t r = 0;
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int t = timer_index(addr);
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/* Make addr relative to this instances base. */
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addr -= t->base;
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switch (addr) {
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case R_TMR0_DATA:
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break;
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@ -113,21 +96,21 @@ static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
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{
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struct timeval now;
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gettimeofday(&now, NULL);
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if (!(timer[t].last.tv_sec == 0
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&& timer[t].last.tv_usec == 0)) {
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r = diff_timeval_us(&now, &timer[t].last);
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if (!(t->last.tv_sec == 0
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&& t->last.tv_usec == 0)) {
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r = diff_timeval_us(&now, &t->last);
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r *= 1000; /* convert to ns. */
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r++; /* make sure we increase for each call. */
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}
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timer[t].last = now;
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t->last = now;
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break;
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}
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case RW_INTR_MASK:
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r = timer[t].rw_intr_mask;
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r = t->rw_intr_mask;
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break;
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case R_MASKED_INTR:
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r = timer[t].r_intr & timer[t].rw_intr_mask;
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r = t->r_intr & t->rw_intr_mask;
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break;
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default:
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D(printf ("%s %x p=%x\n", __func__, addr, env->pc));
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@ -137,18 +120,12 @@ static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
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}
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static void
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timer_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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timer_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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CPUState *env;
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env = opaque;
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D(printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc));
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}
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static void
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timer_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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CPUState *env;
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env = opaque;
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D(printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc));
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struct fs_timer_t *t = opaque;
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CPUState *env = t->env;
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cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
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addr, env->pc);
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}
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static void write_ctrl(struct fs_timer_t *t, uint32_t v)
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@ -212,20 +189,22 @@ static void timer_ack_irq(struct fs_timer_t *t)
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static void
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timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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CPUState *env = opaque;
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int t = timer_index(addr);
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struct fs_timer_t *t = opaque;
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CPUState *env = t->env;
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D(printf ("%s %x %x pc=%x\n",
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__func__, addr, value, env->pc));
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/* Make addr relative to this instances base. */
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addr -= t->base;
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switch (addr)
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{
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case RW_TMR0_DIV:
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D(printf ("RW_TMR0_DIV=%x\n", value));
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timer[t].limit = value;
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t->limit = value;
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break;
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case RW_TMR0_CTRL:
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D(printf ("RW_TMR0_CTRL=%x\n", value));
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write_ctrl(&timer[t], value);
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write_ctrl(t, value);
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break;
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case RW_TMR1_DIV:
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D(printf ("RW_TMR1_DIV=%x\n", value));
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@ -235,14 +214,14 @@ timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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break;
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case RW_INTR_MASK:
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D(printf ("RW_INTR_MASK=%x\n", value));
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timer[t].rw_intr_mask = value;
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t->rw_intr_mask = value;
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break;
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case RW_WD_CTRL:
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D(printf ("RW_WD_CTRL=%x\n", value));
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break;
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case RW_ACK_INTR:
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timer[t].r_intr &= ~value;
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timer_ack_irq(&timer[t]);
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t->r_intr &= ~value;
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timer_ack_irq(t);
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break;
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default:
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printf ("%s %x %x pc=%x\n",
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@ -252,14 +231,14 @@ timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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}
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static CPUReadMemoryFunc *timer_read[] = {
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&timer_readb,
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&timer_readw,
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&timer_rinvalid,
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&timer_rinvalid,
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&timer_readl,
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};
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static CPUWriteMemoryFunc *timer_write[] = {
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&timer_writeb,
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&timer_writew,
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&timer_winvalid,
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&timer_winvalid,
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&timer_writel,
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};
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@ -273,23 +252,23 @@ static void timer_irq(void *opaque)
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}
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}
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void etraxfs_timer_init(CPUState *env, qemu_irq *irqs)
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void etraxfs_timer_init(CPUState *env, qemu_irq *irqs,
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target_phys_addr_t base)
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{
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static struct fs_timer_t *t;
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int timer_regs;
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timer[0].bh = qemu_bh_new(timer_irq, &timer[0]);
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timer[0].ptimer = ptimer_init(timer[0].bh);
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timer[0].irq = irqs + 26;
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timer[0].mask = 1;
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timer[0].env = env;
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t = qemu_mallocz(sizeof *t);
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if (!t)
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return;
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timer[1].bh = qemu_bh_new(timer_irq, &timer[1]);
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timer[1].ptimer = ptimer_init(timer[1].bh);
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timer[1].irq = irqs + 26;
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timer[1].mask = 1;
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timer[1].env = env;
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t->bh = qemu_bh_new(timer_irq, t);
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t->ptimer = ptimer_init(t->bh);
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t->irq = irqs + 26;
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t->mask = 1;
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t->env = env;
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t->base = base;
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timer_regs = cpu_register_io_memory(0, timer_read, timer_write, env);
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cpu_register_physical_memory (0xb001e000, 0x5c, timer_regs);
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cpu_register_physical_memory (0xb005e000, 0x5c, timer_regs);
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timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t);
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cpu_register_physical_memory (base, 0x5c, timer_regs);
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}
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