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plugins/cache: supported multicore cache modelling
Multicore L1 cache modelling is introduced and is supported for both full system emulation and linux-user. For full-system emulation, L1 icache and dcache are maintained for each available core, since this information is exposed to the plugin through `qemu_plugin_n_vcpus()`. For linux-user, a static number of cores is assumed (default 1 core, and can be provided as a plugin argument `cores=N`). Every memory access goes through one of these caches, this approach is taken as it's somewhat akin to what happens on real setup, where a program that dispatches more threads than the available cores, they'll thrash each other Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com> Message-Id: <20210803151301.123581-2-ma.mandourr@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
This commit is contained in:
Mahmoud Mandour
Alex Bennée
parent
b906acace2
commit
c79a2116af
@ -17,18 +17,12 @@ static enum qemu_plugin_mem_rw rw = QEMU_PLUGIN_MEM_RW;
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static GHashTable *miss_ht;
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static GMutex mtx;
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static GMutex hashtable_lock;
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static GRand *rng;
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static int limit;
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static bool sys;
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static uint64_t dmem_accesses;
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static uint64_t dmisses;
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static uint64_t imem_accesses;
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static uint64_t imisses;
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enum EvictionPolicy {
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LRU,
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FIFO,
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@ -80,6 +74,8 @@ typedef struct {
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int blksize_shift;
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uint64_t set_mask;
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uint64_t tag_mask;
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uint64_t accesses;
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uint64_t misses;
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} Cache;
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typedef struct {
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@ -96,7 +92,16 @@ void (*update_miss)(Cache *cache, int set, int blk);
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void (*metadata_init)(Cache *cache);
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void (*metadata_destroy)(Cache *cache);
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Cache *dcache, *icache;
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static int cores;
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static Cache **dcaches, **icaches;
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static GMutex *dcache_locks;
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static GMutex *icache_locks;
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static uint64_t all_dmem_accesses;
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static uint64_t all_imem_accesses;
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static uint64_t all_imisses;
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static uint64_t all_dmisses;
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static int pow_of_two(int num)
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{
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@ -233,20 +238,24 @@ static bool bad_cache_params(int blksize, int assoc, int cachesize)
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static Cache *cache_init(int blksize, int assoc, int cachesize)
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{
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if (bad_cache_params(blksize, assoc, cachesize)) {
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return NULL;
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}
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Cache *cache;
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int i;
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uint64_t blk_mask;
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/*
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* This function shall not be called directly, and hence expects suitable
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* parameters.
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*/
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g_assert(!bad_cache_params(blksize, assoc, cachesize));
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cache = g_new(Cache, 1);
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cache->assoc = assoc;
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cache->cachesize = cachesize;
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cache->num_sets = cachesize / (blksize * assoc);
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cache->sets = g_new(CacheSet, cache->num_sets);
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cache->blksize_shift = pow_of_two(blksize);
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cache->accesses = 0;
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cache->misses = 0;
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for (i = 0; i < cache->num_sets; i++) {
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cache->sets[i].blocks = g_new0(CacheBlock, assoc);
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@ -263,6 +272,24 @@ static Cache *cache_init(int blksize, int assoc, int cachesize)
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return cache;
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}
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static Cache **caches_init(int blksize, int assoc, int cachesize)
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{
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Cache **caches;
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int i;
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if (bad_cache_params(blksize, assoc, cachesize)) {
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return NULL;
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}
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caches = g_new(Cache *, cores);
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for (i = 0; i < cores; i++) {
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caches[i] = cache_init(blksize, assoc, cachesize);
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}
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return caches;
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}
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static int get_invalid_block(Cache *cache, uint64_t set)
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{
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int i;
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@ -353,6 +380,7 @@ static void vcpu_mem_access(unsigned int vcpu_index, qemu_plugin_meminfo_t info,
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{
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uint64_t effective_addr;
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struct qemu_plugin_hwaddr *hwaddr;
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int cache_idx;
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InsnData *insn;
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hwaddr = qemu_plugin_get_hwaddr(info, vaddr);
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@ -361,32 +389,35 @@ static void vcpu_mem_access(unsigned int vcpu_index, qemu_plugin_meminfo_t info,
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}
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effective_addr = hwaddr ? qemu_plugin_hwaddr_phys_addr(hwaddr) : vaddr;
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cache_idx = vcpu_index % cores;
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g_mutex_lock(&mtx);
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if (!access_cache(dcache, effective_addr)) {
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g_mutex_lock(&dcache_locks[cache_idx]);
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if (!access_cache(dcaches[cache_idx], effective_addr)) {
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insn = (InsnData *) userdata;
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insn->dmisses++;
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dmisses++;
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__atomic_fetch_add(&insn->dmisses, 1, __ATOMIC_SEQ_CST);
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dcaches[cache_idx]->misses++;
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}
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dmem_accesses++;
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g_mutex_unlock(&mtx);
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dcaches[cache_idx]->accesses++;
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g_mutex_unlock(&dcache_locks[cache_idx]);
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}
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static void vcpu_insn_exec(unsigned int vcpu_index, void *userdata)
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{
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uint64_t insn_addr;
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InsnData *insn;
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int cache_idx;
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g_mutex_lock(&mtx);
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insn_addr = ((InsnData *) userdata)->addr;
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if (!access_cache(icache, insn_addr)) {
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cache_idx = vcpu_index % cores;
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g_mutex_lock(&icache_locks[cache_idx]);
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if (!access_cache(icaches[cache_idx], insn_addr)) {
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insn = (InsnData *) userdata;
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insn->imisses++;
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imisses++;
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__atomic_fetch_add(&insn->imisses, 1, __ATOMIC_SEQ_CST);
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icaches[cache_idx]->misses++;
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}
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imem_accesses++;
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g_mutex_unlock(&mtx);
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icaches[cache_idx]->accesses++;
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g_mutex_unlock(&icache_locks[cache_idx]);
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}
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static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb)
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@ -411,7 +442,7 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb)
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* new entries for those instructions. Instead, we fetch the same
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* entry from the hash table and register it for the callback again.
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*/
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g_mutex_lock(&mtx);
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g_mutex_lock(&hashtable_lock);
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data = g_hash_table_lookup(miss_ht, GUINT_TO_POINTER(effective_addr));
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if (data == NULL) {
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data = g_new0(InsnData, 1);
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@ -421,7 +452,7 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb)
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g_hash_table_insert(miss_ht, GUINT_TO_POINTER(effective_addr),
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(gpointer) data);
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}
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g_mutex_unlock(&mtx);
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g_mutex_unlock(&hashtable_lock);
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qemu_plugin_register_vcpu_mem_cb(insn, vcpu_mem_access,
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QEMU_PLUGIN_CB_NO_REGS,
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@ -453,6 +484,15 @@ static void cache_free(Cache *cache)
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g_free(cache);
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}
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static void caches_free(Cache **caches)
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{
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int i;
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for (i = 0; i < cores; i++) {
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cache_free(caches[i]);
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}
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}
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static int dcmp(gconstpointer a, gconstpointer b)
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{
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InsnData *insn_a = (InsnData *) a;
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@ -461,6 +501,37 @@ static int dcmp(gconstpointer a, gconstpointer b)
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return insn_a->dmisses < insn_b->dmisses ? 1 : -1;
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}
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static void append_stats_line(GString *line, uint64_t daccess, uint64_t dmisses,
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uint64_t iaccess, uint64_t imisses)
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{
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double dmiss_rate, imiss_rate;
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dmiss_rate = ((double) dmisses) / (daccess) * 100.0;
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imiss_rate = ((double) imisses) / (iaccess) * 100.0;
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g_string_append_printf(line, "%-14lu %-12lu %9.4lf%% %-14lu %-12lu"
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" %9.4lf%%\n",
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daccess,
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dmisses,
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daccess ? dmiss_rate : 0.0,
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iaccess,
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imisses,
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iaccess ? imiss_rate : 0.0);
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}
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static void sum_stats(void)
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{
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int i;
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g_assert(cores > 1);
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for (i = 0; i < cores; i++) {
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all_imisses += icaches[i]->misses;
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all_dmisses += dcaches[i]->misses;
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all_imem_accesses += icaches[i]->accesses;
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all_dmem_accesses += dcaches[i]->accesses;
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}
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}
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static int icmp(gconstpointer a, gconstpointer b)
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{
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InsnData *insn_a = (InsnData *) a;
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@ -471,19 +542,29 @@ static int icmp(gconstpointer a, gconstpointer b)
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static void log_stats(void)
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{
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g_autoptr(GString) rep = g_string_new("");
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g_string_append_printf(rep,
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"Data accesses: %lu, Misses: %lu\nMiss rate: %lf%%\n\n",
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dmem_accesses,
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dmisses,
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((double) dmisses / (double) dmem_accesses) * 100.0);
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int i;
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Cache *icache, *dcache;
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g_string_append_printf(rep,
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"Instruction accesses: %lu, Misses: %lu\nMiss rate: %lf%%\n\n",
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imem_accesses,
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imisses,
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((double) imisses / (double) imem_accesses) * 100.0);
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g_autoptr(GString) rep = g_string_new("core #, data accesses, data misses,"
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" dmiss rate, insn accesses,"
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" insn misses, imiss rate\n");
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for (i = 0; i < cores; i++) {
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g_string_append_printf(rep, "%-8d", i);
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dcache = dcaches[i];
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icache = icaches[i];
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append_stats_line(rep, dcache->accesses, dcache->misses,
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icache->accesses, icache->misses);
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}
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if (cores > 1) {
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sum_stats();
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g_string_append_printf(rep, "%-8s", "sum");
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append_stats_line(rep, all_dmem_accesses, all_dmisses,
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all_imem_accesses, all_imisses);
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}
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g_string_append(rep, "\n");
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qemu_plugin_outs(rep->str);
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}
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@ -530,8 +611,8 @@ static void plugin_exit(qemu_plugin_id_t id, void *p)
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log_stats();
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log_top_insns();
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cache_free(dcache);
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cache_free(icache);
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caches_free(dcaches);
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caches_free(icaches);
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g_hash_table_destroy(miss_ht);
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}
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@ -579,6 +660,8 @@ int qemu_plugin_install(qemu_plugin_id_t id, const qemu_info_t *info,
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policy = LRU;
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cores = sys ? qemu_plugin_n_vcpus() : 1;
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for (i = 0; i < argc; i++) {
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char *opt = argv[i];
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if (g_str_has_prefix(opt, "iblksize=")) {
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@ -595,6 +678,8 @@ int qemu_plugin_install(qemu_plugin_id_t id, const qemu_info_t *info,
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dcachesize = g_ascii_strtoll(opt + 11, NULL, 10);
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} else if (g_str_has_prefix(opt, "limit=")) {
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limit = g_ascii_strtoll(opt + 6, NULL, 10);
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} else if (g_str_has_prefix(opt, "cores=")) {
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cores = g_ascii_strtoll(opt + 6, NULL, 10);
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} else if (g_str_has_prefix(opt, "evict=")) {
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gchar *p = opt + 6;
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if (g_strcmp0(p, "rand") == 0) {
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@ -615,22 +700,25 @@ int qemu_plugin_install(qemu_plugin_id_t id, const qemu_info_t *info,
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policy_init();
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dcache = cache_init(dblksize, dassoc, dcachesize);
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if (!dcache) {
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dcaches = caches_init(dblksize, dassoc, dcachesize);
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if (!dcaches) {
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const char *err = cache_config_error(dblksize, dassoc, dcachesize);
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fprintf(stderr, "dcache cannot be constructed from given parameters\n");
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fprintf(stderr, "%s\n", err);
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return -1;
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}
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icache = cache_init(iblksize, iassoc, icachesize);
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if (!icache) {
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icaches = caches_init(iblksize, iassoc, icachesize);
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if (!icaches) {
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const char *err = cache_config_error(iblksize, iassoc, icachesize);
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fprintf(stderr, "icache cannot be constructed from given parameters\n");
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fprintf(stderr, "%s\n", err);
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return -1;
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}
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dcache_locks = g_new0(GMutex, cores);
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icache_locks = g_new0(GMutex, cores);
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qemu_plugin_register_vcpu_tb_trans_cb(id, vcpu_tb_trans);
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qemu_plugin_register_atexit_cb(id, plugin_exit, NULL);
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