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dp8393x: fix dp8393x_receive()

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RXpkt.in_use is always 16 bit wide, but when the bus access mode is 32bit
and the endianness is big, we must access the second word and not the
first. This patch adjusts the offset according to the size and endianness.

This fixes DHCP for Q800 guest.

Fixes: be92084198 ("dp8393x: manage big endian bus")
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Tested-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20191106112341.23735-3-laurent@vivier.eu>
This commit is contained in:
Laurent Vivier 2019-11-06 12:23:41 +01:00
parent af9f0be36c
commit c744cf7879
1 changed files with 9 additions and 3 deletions
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12
hw/net/dp8393x.c
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@ -831,9 +831,15 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
/* EOL detected */ /* EOL detected */
s->regs[SONIC_ISR] |= SONIC_ISR_RDE; s->regs[SONIC_ISR] |= SONIC_ISR_RDE;
} else { } else {
dp8393x_put(s, width, 0, 0); /* in_use */ /* Clear in_use, but it is always 16bit wide */
address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 6 * width, int offset = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width;
MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, sizeof(uint16_t), 1); if (s->big_endian && width == 2) {
/* we need to adjust the offset of the 16bit field */
offset += sizeof(uint16_t);
}
s->data[0] = 0;
address_space_rw(&s->as, offset, MEMTXATTRS_UNSPECIFIED,
(uint8_t *)s->data, sizeof(uint16_t), 1);
s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX; s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff); s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff);