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target/riscv/cpu: set cpu->cfg in register_cpu_props()
There is an informal contract between the cpu_init() functions and riscv_cpu_realize(): if cpu->env.misa_ext is zero, assume that the default settings were loaded via register_cpu_props() and do validations to set env.misa_ext. If it's not zero, skip this whole process and assume that the board somehow did everything. At this moment, all SiFive CPUs are setting a non-zero misa_ext during their cpu_init() and skipping a good chunk of riscv_cpu_realize(). This causes problems when the code being skipped in riscv_cpu_realize() contains fixes or assumptions that affects all CPUs, meaning that SiFive CPUs are missing out. To allow this code to not be skipped anymore, all the cpu->cfg.ext_* attributes needs to be set during cpu_init() time. At this moment this is being done in register_cpu_props(). The SiFive boards are setting their own extensions during cpu_init() though, meaning that they don't want all the defaults from register_cpu_props(). Let's move the contract between *_cpu_init() and riscv_cpu_realize() to register_cpu_props(). Inside this function we'll check if cpu->env.misa_ext was set and, if that's the case, set all relevant cpu->cfg.ext_* attributes, and only that. Leave the 'misa_ext' = 0 case as is today, i.e. loading all the defaults from riscv_cpu_extensions[]. register_cpu_props() can then be called by all the cpu_init() functions, including the SiFive ones. This will make all CPUs behave more in line with what riscv_cpu_realize() expects. This will also make the cpu_init() functions even more alike, but at this moment we would need some design changes in how we're initializing extensions/attributes (e.g. some CPUs are setting cfg options after register_cpu_props(), so we can't simply add the function to a common post_init() hook) to make a common cpu_init() code across all CPUs. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230113175230.473975-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -256,6 +256,7 @@ static void rv64_sifive_u_cpu_init(Object *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
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register_cpu_props(DEVICE(obj));
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set_priv_version(env, PRIV_VERSION_1_10_0);
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}
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@ -265,6 +266,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
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RISCVCPU *cpu = RISCV_CPU(obj);
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set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
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register_cpu_props(DEVICE(obj));
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set_priv_version(env, PRIV_VERSION_1_10_0);
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cpu->cfg.mmu = false;
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}
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@ -299,6 +301,7 @@ static void rv32_sifive_u_cpu_init(Object *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
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register_cpu_props(DEVICE(obj));
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set_priv_version(env, PRIV_VERSION_1_10_0);
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}
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@ -308,6 +311,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)
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RISCVCPU *cpu = RISCV_CPU(obj);
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set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
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register_cpu_props(DEVICE(obj));
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set_priv_version(env, PRIV_VERSION_1_10_0);
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cpu->cfg.mmu = false;
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}
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@ -318,6 +322,7 @@ static void rv32_ibex_cpu_init(Object *obj)
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RISCVCPU *cpu = RISCV_CPU(obj);
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set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
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register_cpu_props(DEVICE(obj));
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set_priv_version(env, PRIV_VERSION_1_11_0);
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cpu->cfg.mmu = false;
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cpu->cfg.epmp = true;
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@ -329,6 +334,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
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RISCVCPU *cpu = RISCV_CPU(obj);
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set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
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register_cpu_props(DEVICE(obj));
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set_priv_version(env, PRIV_VERSION_1_10_0);
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cpu->cfg.mmu = false;
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}
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@ -1083,10 +1089,44 @@ static Property riscv_cpu_extensions[] = {
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DEFINE_PROP_END_OF_LIST(),
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};
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/*
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* Register CPU props based on env.misa_ext. If a non-zero
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* value was set, register only the required cpu->cfg.ext_*
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* properties and leave. env.misa_ext = 0 means that we want
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* all the default properties to be registered.
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*/
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static void register_cpu_props(DeviceState *dev)
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{
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RISCVCPU *cpu = RISCV_CPU(OBJECT(dev));
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uint32_t misa_ext = cpu->env.misa_ext;
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Property *prop;
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/*
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* If misa_ext is not zero, set cfg properties now to
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* allow them to be read during riscv_cpu_realize()
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* later on.
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*/
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if (cpu->env.misa_ext != 0) {
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cpu->cfg.ext_i = misa_ext & RVI;
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cpu->cfg.ext_e = misa_ext & RVE;
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cpu->cfg.ext_m = misa_ext & RVM;
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cpu->cfg.ext_a = misa_ext & RVA;
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cpu->cfg.ext_f = misa_ext & RVF;
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cpu->cfg.ext_d = misa_ext & RVD;
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cpu->cfg.ext_v = misa_ext & RVV;
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cpu->cfg.ext_c = misa_ext & RVC;
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cpu->cfg.ext_s = misa_ext & RVS;
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cpu->cfg.ext_u = misa_ext & RVU;
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cpu->cfg.ext_h = misa_ext & RVH;
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cpu->cfg.ext_j = misa_ext & RVJ;
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/*
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* We don't want to set the default riscv_cpu_extensions
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* in this case.
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*/
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return;
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}
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for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
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qdev_property_add_static(dev, prop);
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}
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@ -63,6 +63,10 @@
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#define RV(x) ((target_ulong)1 << (x - 'A'))
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/*
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* Consider updating register_cpu_props() when adding
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* new MISA bits here.
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*/
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#define RVI RV('I')
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#define RVE RV('E') /* E and I are mutually exclusive */
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#define RVM RV('M')
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