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target/sparc: Split out ldst functions with asi pre-computed
As an intermediate step in decodetree conversion, create new functions passing in DisasASI and not insn. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
a76779ee3b
commit
c03a0fd15c
@ -2162,25 +2162,21 @@ static void gen_helper_st_asi(TCGv_env e, TCGv a, TCGv_i64 r,
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}
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#endif
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static void __attribute__((unused))
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gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn, MemOp memop)
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static void gen_ld_asi0(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr)
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{
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DisasASI da = get_asi(dc, insn, memop);
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switch (da.type) {
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switch (da->type) {
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case GET_ASI_EXCP:
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break;
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case GET_ASI_DTWINX: /* Reserved for ldda. */
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gen_exception(dc, TT_ILL_INSN);
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break;
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case GET_ASI_DIRECT:
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gen_address_mask(dc, addr);
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tcg_gen_qemu_ld_tl(dst, addr, da.mem_idx, da.memop | MO_ALIGN);
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tcg_gen_qemu_ld_tl(dst, addr, da->mem_idx, da->memop | MO_ALIGN);
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break;
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default:
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{
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TCGv_i32 r_asi = tcg_constant_i32(da.asi);
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TCGv_i32 r_mop = tcg_constant_i32(memop | MO_ALIGN);
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TCGv_i32 r_asi = tcg_constant_i32(da->asi);
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TCGv_i32 r_mop = tcg_constant_i32(da->memop | MO_ALIGN);
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save_state(dc);
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#ifdef TARGET_SPARC64
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@ -2198,33 +2194,38 @@ gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn, MemOp memop)
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}
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static void __attribute__((unused))
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gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, int insn, MemOp memop)
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gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn, MemOp memop)
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{
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DisasASI da = get_asi(dc, insn, memop);
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switch (da.type) {
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gen_address_mask(dc, addr);
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gen_ld_asi0(dc, &da, dst, addr);
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}
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static void gen_st_asi0(DisasContext *dc, DisasASI *da, TCGv src, TCGv addr)
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{
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switch (da->type) {
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case GET_ASI_EXCP:
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break;
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case GET_ASI_DTWINX: /* Reserved for stda. */
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#ifndef TARGET_SPARC64
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gen_exception(dc, TT_ILL_INSN);
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break;
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#else
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if (!(dc->def->features & CPU_FEATURE_HYPV)) {
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if (TARGET_LONG_BITS == 32) {
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gen_exception(dc, TT_ILL_INSN);
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break;
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} else if (!(dc->def->features & CPU_FEATURE_HYPV)) {
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/* Pre OpenSPARC CPUs don't have these */
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gen_exception(dc, TT_ILL_INSN);
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return;
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break;
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}
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/* in OpenSPARC T1+ CPUs TWINX ASIs in store instructions
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* are ST_BLKINIT_ ASIs */
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#endif
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/* In OpenSPARC T1+ CPUs TWINX ASIs in store are ST_BLKINIT_ ASIs */
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/* fall through */
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case GET_ASI_DIRECT:
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gen_address_mask(dc, addr);
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tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop | MO_ALIGN);
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tcg_gen_qemu_st_tl(src, addr, da->mem_idx, da->memop | MO_ALIGN);
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break;
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#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
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case GET_ASI_BCOPY:
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assert(TARGET_LONG_BITS == 32);
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/* Copy 32 bytes from the address in SRC to ADDR. */
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/* ??? The original qemu code suggests 4-byte alignment, dropping
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the low bits, but the only place I can see this used is in the
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@ -2242,18 +2243,18 @@ gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, int insn, MemOp memop)
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for (i = 0; i < 32; i += 4) {
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/* Since the loads and stores are paired, allow the
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copy to happen in the host endianness. */
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tcg_gen_qemu_ld_i32(tmp, saddr, da.mem_idx, MO_UL);
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tcg_gen_qemu_st_i32(tmp, daddr, da.mem_idx, MO_UL);
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tcg_gen_qemu_ld_i32(tmp, saddr, da->mem_idx, MO_UL);
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tcg_gen_qemu_st_i32(tmp, daddr, da->mem_idx, MO_UL);
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tcg_gen_add_tl(saddr, saddr, four);
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tcg_gen_add_tl(daddr, daddr, four);
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}
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}
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break;
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#endif
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default:
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{
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TCGv_i32 r_asi = tcg_constant_i32(da.asi);
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TCGv_i32 r_mop = tcg_constant_i32(memop | MO_ALIGN);
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TCGv_i32 r_asi = tcg_constant_i32(da->asi);
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TCGv_i32 r_mop = tcg_constant_i32(da->memop | MO_ALIGN);
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save_state(dc);
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#ifdef TARGET_SPARC64
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@ -2273,16 +2274,49 @@ gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, int insn, MemOp memop)
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}
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}
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static void __attribute__((unused))
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gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, int insn, MemOp memop)
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{
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DisasASI da = get_asi(dc, insn, memop);
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gen_address_mask(dc, addr);
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gen_st_asi0(dc, &da, src, addr);
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}
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static void gen_swap_asi0(DisasContext *dc, DisasASI *da,
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TCGv dst, TCGv src, TCGv addr)
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{
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switch (da->type) {
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case GET_ASI_EXCP:
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break;
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case GET_ASI_DIRECT:
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gen_swap(dc, dst, src, addr, da->mem_idx, da->memop);
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break;
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default:
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/* ??? Should be DAE_invalid_asi. */
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gen_exception(dc, TT_DATA_ACCESS);
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break;
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}
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}
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static void __attribute__((unused))
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gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src, TCGv addr, int insn)
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{
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DisasASI da = get_asi(dc, insn, MO_TEUL);
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switch (da.type) {
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gen_address_mask(dc, addr);
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gen_swap_asi0(dc, &da, dst, src, addr);
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}
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static void gen_cas_asi0(DisasContext *dc, DisasASI *da,
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TCGv oldv, TCGv newv, TCGv cmpv, TCGv addr)
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{
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switch (da->type) {
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case GET_ASI_EXCP:
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break;
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return;
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case GET_ASI_DIRECT:
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gen_swap(dc, dst, src, addr, da.mem_idx, da.memop);
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tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, newv,
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da->mem_idx, da->memop | MO_ALIGN);
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break;
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default:
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/* ??? Should be DAE_invalid_asi. */
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@ -2295,34 +2329,33 @@ static void __attribute__((unused))
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gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd)
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{
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DisasASI da = get_asi(dc, insn, MO_TEUL);
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TCGv oldv;
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TCGv oldv = gen_dest_gpr(dc, rd);
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TCGv newv = gen_load_gpr(dc, rd);
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switch (da.type) {
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case GET_ASI_EXCP:
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return;
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case GET_ASI_DIRECT:
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oldv = tcg_temp_new();
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tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd),
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da.mem_idx, da.memop | MO_ALIGN);
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gen_store_gpr(dc, rd, oldv);
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break;
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default:
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/* ??? Should be DAE_invalid_asi. */
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gen_exception(dc, TT_DATA_ACCESS);
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break;
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}
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gen_address_mask(dc, addr);
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gen_cas_asi0(dc, &da, oldv, newv, cmpv, addr);
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gen_store_gpr(dc, rd, oldv);
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}
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static void __attribute__((unused))
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gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
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gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd)
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{
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DisasASI da = get_asi(dc, insn, MO_UB);
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DisasASI da = get_asi(dc, insn, MO_TEUQ);
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TCGv oldv = gen_dest_gpr(dc, rd);
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TCGv newv = gen_load_gpr(dc, rd);
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switch (da.type) {
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gen_address_mask(dc, addr);
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gen_cas_asi0(dc, &da, oldv, newv, cmpv, addr);
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gen_store_gpr(dc, rd, oldv);
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}
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static void gen_ldstub_asi0(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr)
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{
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switch (da->type) {
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case GET_ASI_EXCP:
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break;
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case GET_ASI_DIRECT:
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gen_ldstub(dc, dst, addr, da.mem_idx);
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gen_ldstub(dc, dst, addr, da->mem_idx);
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break;
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default:
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/* ??? In theory, this should be raise DAE_invalid_asi.
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@ -2330,7 +2363,7 @@ gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
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if (tb_cflags(dc->base.tb) & CF_PARALLEL) {
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gen_helper_exit_atomic(tcg_env);
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} else {
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TCGv_i32 r_asi = tcg_constant_i32(da.asi);
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TCGv_i32 r_asi = tcg_constant_i32(da->asi);
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TCGv_i32 r_mop = tcg_constant_i32(MO_UB);
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TCGv_i64 s64, t64;
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@ -2350,6 +2383,15 @@ gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
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}
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}
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static void __attribute__((unused))
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gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
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{
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DisasASI da = get_asi(dc, insn, MO_UB);
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gen_address_mask(dc, addr);
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gen_ldstub_asi0(dc, &da, dst, addr);
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}
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static void __attribute__((unused))
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gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
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{
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@ -2542,36 +2584,32 @@ gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
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}
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}
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static void __attribute__((unused))
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gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
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static void gen_ldda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
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{
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DisasASI da = get_asi(dc, insn, MO_TEUQ);
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TCGv hi = gen_dest_gpr(dc, rd);
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TCGv lo = gen_dest_gpr(dc, rd + 1);
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switch (da.type) {
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switch (da->type) {
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case GET_ASI_EXCP:
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return;
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case GET_ASI_DTWINX:
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assert(TARGET_LONG_BITS == 64);
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gen_address_mask(dc, addr);
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tcg_gen_qemu_ld_tl(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
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tcg_gen_qemu_ld_tl(hi, addr, da->mem_idx, da->memop | MO_ALIGN_16);
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tcg_gen_addi_tl(addr, addr, 8);
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tcg_gen_qemu_ld_tl(lo, addr, da.mem_idx, da.memop);
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tcg_gen_qemu_ld_tl(lo, addr, da->mem_idx, da->memop);
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break;
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case GET_ASI_DIRECT:
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{
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TCGv_i64 tmp = tcg_temp_new_i64();
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gen_address_mask(dc, addr);
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tcg_gen_qemu_ld_i64(tmp, addr, da.mem_idx, da.memop | MO_ALIGN);
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tcg_gen_qemu_ld_i64(tmp, addr, da->mem_idx, da->memop | MO_ALIGN);
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/* Note that LE ldda acts as if each 32-bit register
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result is byte swapped. Having just performed one
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64-bit bswap, we need now to swap the writebacks. */
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if ((da.memop & MO_BSWAP) == MO_TE) {
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if ((da->memop & MO_BSWAP) == MO_TE) {
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tcg_gen_extr_i64_tl(lo, hi, tmp);
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} else {
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tcg_gen_extr_i64_tl(hi, lo, tmp);
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@ -2585,15 +2623,15 @@ gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
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real hardware allows others. This can be seen with e.g.
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FreeBSD 10.3 wrt ASI_IC_TAG. */
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{
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TCGv_i32 r_asi = tcg_constant_i32(da.asi);
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TCGv_i32 r_mop = tcg_constant_i32(da.memop);
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TCGv_i32 r_asi = tcg_constant_i32(da->asi);
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TCGv_i32 r_mop = tcg_constant_i32(da->memop);
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TCGv_i64 tmp = tcg_temp_new_i64();
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save_state(dc);
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gen_helper_ld_asi(tmp, tcg_env, addr, r_asi, r_mop);
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/* See above. */
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if ((da.memop & MO_BSWAP) == MO_TE) {
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if ((da->memop & MO_BSWAP) == MO_TE) {
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tcg_gen_extr_i64_tl(lo, hi, tmp);
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} else {
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tcg_gen_extr_i64_tl(hi, lo, tmp);
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@ -2607,21 +2645,28 @@ gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
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}
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static void __attribute__((unused))
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gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd)
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gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
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{
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DisasASI da = get_asi(dc, insn, MO_TEUQ);
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gen_address_mask(dc, addr);
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gen_ldda_asi0(dc, &da, addr, rd);
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}
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static void gen_stda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
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{
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TCGv hi = gen_load_gpr(dc, rd);
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TCGv lo = gen_load_gpr(dc, rd + 1);
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switch (da.type) {
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switch (da->type) {
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case GET_ASI_EXCP:
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break;
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case GET_ASI_DTWINX:
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assert(TARGET_LONG_BITS == 64);
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gen_address_mask(dc, addr);
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tcg_gen_qemu_st_tl(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
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tcg_gen_qemu_st_tl(hi, addr, da->mem_idx, da->memop | MO_ALIGN_16);
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tcg_gen_addi_tl(addr, addr, 8);
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tcg_gen_qemu_st_tl(lo, addr, da.mem_idx, da.memop);
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tcg_gen_qemu_st_tl(lo, addr, da->mem_idx, da->memop);
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break;
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case GET_ASI_DIRECT:
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@ -2631,13 +2676,12 @@ gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd)
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/* Note that LE stda acts as if each 32-bit register result is
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byte swapped. We will perform one 64-bit LE store, so now
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we must swap the order of the construction. */
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if ((da.memop & MO_BSWAP) == MO_TE) {
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if ((da->memop & MO_BSWAP) == MO_TE) {
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tcg_gen_concat_tl_i64(t64, lo, hi);
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} else {
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tcg_gen_concat_tl_i64(t64, hi, lo);
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}
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gen_address_mask(dc, addr);
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tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN);
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tcg_gen_qemu_st_i64(t64, addr, da->mem_idx, da->memop | MO_ALIGN);
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}
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break;
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@ -2657,7 +2701,7 @@ gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd)
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tcg_gen_concat_tl_i64(t64, lo, hi);
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tcg_gen_andi_tl(d_addr, addr, -8);
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for (i = 0; i < 32; i += 8) {
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tcg_gen_qemu_st_i64(t64, d_addr, da.mem_idx, da.memop);
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tcg_gen_qemu_st_i64(t64, d_addr, da->mem_idx, da->memop);
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tcg_gen_add_tl(d_addr, d_addr, eight);
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}
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}
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@ -2667,12 +2711,12 @@ gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd)
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/* ??? In theory we've handled all of the ASIs that are valid
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for stda, and this should raise DAE_invalid_asi. */
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{
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TCGv_i32 r_asi = tcg_constant_i32(da.asi);
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TCGv_i32 r_mop = tcg_constant_i32(da.memop);
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TCGv_i32 r_asi = tcg_constant_i32(da->asi);
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TCGv_i32 r_mop = tcg_constant_i32(da->memop);
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TCGv_i64 t64 = tcg_temp_new_i64();
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/* See above. */
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if ((da.memop & MO_BSWAP) == MO_TE) {
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if ((da->memop & MO_BSWAP) == MO_TE) {
|
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tcg_gen_concat_tl_i64(t64, lo, hi);
|
||||
} else {
|
||||
tcg_gen_concat_tl_i64(t64, hi, lo);
|
||||
@ -2686,25 +2730,12 @@ gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd)
|
||||
}
|
||||
|
||||
static void __attribute__((unused))
|
||||
gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd)
|
||||
gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd)
|
||||
{
|
||||
DisasASI da = get_asi(dc, insn, MO_TEUQ);
|
||||
TCGv oldv;
|
||||
|
||||
switch (da.type) {
|
||||
case GET_ASI_EXCP:
|
||||
return;
|
||||
case GET_ASI_DIRECT:
|
||||
oldv = tcg_temp_new();
|
||||
tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd),
|
||||
da.mem_idx, da.memop | MO_ALIGN);
|
||||
gen_store_gpr(dc, rd, oldv);
|
||||
break;
|
||||
default:
|
||||
/* ??? Should be DAE_invalid_asi. */
|
||||
gen_exception(dc, TT_DATA_ACCESS);
|
||||
break;
|
||||
}
|
||||
gen_address_mask(dc, addr);
|
||||
gen_stda_asi0(dc, &da, addr, rd);
|
||||
}
|
||||
|
||||
static TCGv get_src1(DisasContext *dc, unsigned int insn)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user