mirrors/qemu
0
0
Fork 0
mirror of https://github.com/qemu/qemu.git synced 2024-11-24 11:23:43 +08:00
Code Issues Packages Projects Releases Wiki Activity

Clean up of some target specifics in exec.c/cpu-exec.c.

Browse Source 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2936 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-06-03 17:44:37 +00:00
parent 08ab123c2d
commit bfed01fc79
12 changed files with 92 additions and 92 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

69
cpu-exec.c
View File

@ -40,14 +40,14 @@ int tb_invalidated_flag;
//#define DEBUG_EXEC
//#define DEBUG_SIGNAL
#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_M68K) || \
defined(TARGET_ALPHA)
/* XXX: unify with i386 target */
void cpu_loop_exit(void)
{
/* NOTE: the register at this point must be saved by hand because
longjmp restore them */
regs_to_env();
longjmp(env->jmp_env, 1);
}
#endif
#if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
#define reg_T2
#endif
@ -249,65 +249,8 @@ int cpu_exec(CPUState *env1)
TranslationBlock *tb;
uint8_t *tc_ptr;
#if defined(TARGET_I386)
/* handle exit of HALTED state */
if (env1->hflags & HF_HALTED_MASK) {
/* disable halt condition */
if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
(env1->eflags & IF_MASK)) {
env1->hflags &= ~HF_HALTED_MASK;
} else {
return EXCP_HALTED;
}
}
#elif defined(TARGET_PPC)
if (env1->halted) {
if (env1->msr[MSR_EE] &&
(env1->interrupt_request & CPU_INTERRUPT_HARD)) {
env1->halted = 0;
} else {
return EXCP_HALTED;
}
}
#elif defined(TARGET_SPARC)
if (env1->halted) {
if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
(env1->psret != 0)) {
env1->halted = 0;
} else {
return EXCP_HALTED;
}
}
#elif defined(TARGET_ARM)
if (env1->halted) {
/* An interrupt wakes the CPU even if the I and F CPSR bits are
set. We use EXITTB to silently wake CPU without causing an
actual interrupt. */
if (env1->interrupt_request &
(CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB)) {
env1->halted = 0;
} else {
return EXCP_HALTED;
}
}
#elif defined(TARGET_MIPS)
if (env1->halted) {
if (env1->interrupt_request &
(CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
env1->halted = 0;
} else {
return EXCP_HALTED;
}
}
#elif defined(TARGET_ALPHA) || defined(TARGET_M68K)
if (env1->halted) {
if (env1->interrupt_request & CPU_INTERRUPT_HARD) {
env1->halted = 0;
} else {
return EXCP_HALTED;
}
}
#endif
if (cpu_halted(env1) == EXCP_HALTED)
return EXCP_HALTED;
cpu_single_env = env1;

10
target-alpha/exec.h
View File

@ -79,4 +79,14 @@ int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp);
void do_interrupt (CPUState *env);
static inline int cpu_halted(CPUState *env) {
if (!env->halted)
return 0;
if (env->interrupt_request & CPU_INTERRUPT_HARD) {
env->halted = 0;
return 0;
}
return EXCP_HALTED;
}
#endif /* !defined (__ALPHA_EXEC_H__) */

14
target-arm/exec.h
View File

@ -48,6 +48,20 @@ static inline void regs_to_env(void)
int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int is_user, int is_softmmu);
static inline int cpu_halted(CPUState *env) {
if (!env->halted)
return 0;
/* An interrupt wakes the CPU even if the I and F CPSR bits are
set. We use EXITTB to silently wake CPU without causing an
actual interrupt. */
if (env->interrupt_request &
(CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB)) {
env->halted = 0;
return 0;
}
return EXCP_HALTED;
}
#if !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"
#endif

13
target-i386/exec.h
View File

@ -575,3 +575,16 @@ static inline void regs_to_env(void)
env->regs[R_EDI] = EDI;
#endif
}
static inline int cpu_halted(CPUState *env) {
/* handle exit of HALTED state */
if (env->hflags & HF_HALTED_MASK)
return 0;
/* disable halt condition */
if ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
(env->eflags & IF_MASK)) {
env->hflags &= ~HF_HALTED_MASK;
return 0;
}
return EXCP_HALTED;
}

8
target-i386/helper.c
View File

@ -106,14 +106,6 @@ void cpu_unlock(void)
spin_unlock(&global_cpu_lock);
}
void cpu_loop_exit(void)
{
/* NOTE: the register at this point must be saved by hand because
longjmp restore them */
regs_to_env();
longjmp(env->jmp_env, 1);
}
/* return non zero if error */
static inline int load_segment(uint32_t *e1_ptr, uint32_t *e2_ptr,
int selector)

10
target-m68k/exec.h
View File

@ -49,3 +49,13 @@ float64 helper_sub_cmpf64(CPUM68KState *env, float64 src0, float64 src1);
void helper_movec(CPUM68KState *env, int reg, uint32_t val);
void cpu_loop_exit(void);
static inline int cpu_halted(CPUState *env) {
if (!env->halted)
return 0;
if (env->interrupt_request & CPU_INTERRUPT_HARD) {
env->halted = 0;
return 0;
}
return EXCP_HALTED;
}

27
target-mips/exec.h
View File

@ -56,14 +56,6 @@ register target_ulong T2 asm(AREG3);
#include "softmmu_exec.h"
#endif /* !defined(CONFIG_USER_ONLY) */
static inline void env_to_regs(void)
{
}
static inline void regs_to_env(void)
{
}
#ifdef TARGET_MIPS64
#if TARGET_LONG_BITS > HOST_LONG_BITS
void do_dsll (void);
@ -240,4 +232,23 @@ FOP_PROTO(le)
FOP_PROTO(ngt)
#undef FOP_PROTO
static inline void env_to_regs(void)
{
}
static inline void regs_to_env(void)
{
}
static inline int cpu_halted(CPUState *env) {
if (!env->halted)
return 0;
if (env->interrupt_request &
(CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
env->halted = 0;
return 0;
}
return EXCP_HALTED;
}
#endif /* !defined(__QEMU_MIPS_EXEC_H__) */

4
target-mips/op_helper.c
View File

@ -24,10 +24,6 @@
/*****************************************************************************/
/* Exceptions processing helpers */
void cpu_loop_exit(void)
{
longjmp(env->jmp_env, 1);
}
void do_raise_exception_err (uint32_t exception, int error_code)
{

10
target-ppc/exec.h
View File

@ -122,4 +122,14 @@ static inline void regs_to_env(void)
int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int is_user, int is_softmmu);
static inline int cpu_halted(CPUState *env) {
if (!env->halted)
return 0;
if (env->msr[MSR_EE] && (env->interrupt_request & CPU_INTERRUPT_HARD)) {
env->halted = 0;
return 0;
}
return EXCP_HALTED;
}
#endif /* !defined (__PPC_H__) */

4
target-ppc/op_helper.c
View File

@ -40,10 +40,6 @@
/*****************************************************************************/
/* Exceptions processing helpers */
void cpu_loop_exit (void)
{
longjmp(env->jmp_env, 1);
}
void do_raise_exception_err (uint32_t exception, int error_code)
{

5
target-sh4/op_helper.c
View File

@ -20,11 +20,6 @@
#include <assert.h>
#include "exec.h"
void cpu_loop_exit(void)
{
longjmp(env->jmp_env, 1);
}
void do_raise_exception(void)
{
cpu_loop_exit();

10
target-sparc/exec.h
View File

@ -115,4 +115,14 @@ static inline void regs_to_env(void)
int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
int is_user, int is_softmmu);
static inline int cpu_halted(CPUState *env) {
if (!env->halted)
return 0;
if ((env->interrupt_request & CPU_INTERRUPT_HARD) && (env->psret != 0)) {
env->halted = 0;
return 0;
}
return EXCP_HALTED;
}
#endif