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qdev: use device_class_set_parent_realize/unrealize/reset()

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changes generated using the following Coccinelle patch:

  @@
  type DeviceParentClass;
  DeviceParentClass *pc;
  DeviceClass *dc;
  identifier parent_fn;
  identifier child_fn;
  @@
  (
  +device_class_set_parent_realize(dc, child_fn, &pc->parent_fn);
  -pc->parent_fn = dc->realize;
  ...
  -dc->realize = child_fn;
  |
  +device_class_set_parent_unrealize(dc, child_fn, &pc->parent_fn);
  -pc->parent_fn = dc->unrealize;
  ...
  -dc->unrealize = child_fn;
  |
  +device_class_set_parent_reset(dc, child_fn, &pc->parent_fn);
  -pc->parent_fn = dc->reset;
  ...
  -dc->reset = child_fn;
  )

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20180114020412.26160-4-f4bug@amsat.org>
Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Philippe Mathieu-Daudé 2018-01-13 23:04:12 -03:00 committed by Paolo Bonzini
parent 46795cf2e2
commit bf85388169
37 changed files with 73 additions and 88 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
hw/i386/kvm/i8254.c
View File

@ -315,8 +315,8 @@ static void kvm_pit_class_init(ObjectClass *klass, void *data)
PITCommonClass *k = PIT_COMMON_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
kpc->parent_realize = dc->realize;
dc->realize = kvm_pit_realizefn;
device_class_set_parent_realize(dc, kvm_pit_realizefn,
&kpc->parent_realize);
k->set_channel_gate = kvm_pit_set_gate;
k->get_channel_info = kvm_pit_get_channel_info;
dc->reset = kvm_pit_reset;

3
hw/i386/kvm/i8259.c
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@ -142,8 +142,7 @@ static void kvm_i8259_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = kvm_pic_reset;
kpc->parent_realize = dc->realize;
dc->realize = kvm_pic_realize;
device_class_set_parent_realize(dc, kvm_pic_realize, &kpc->parent_realize);
k->pre_save = kvm_pic_get;
k->post_load = kvm_pic_put;
}

4
hw/input/adb-kbd.c
View File

@ -374,8 +374,8 @@ static void adb_kbd_class_init(ObjectClass *oc, void *data)
ADBDeviceClass *adc = ADB_DEVICE_CLASS(oc);
ADBKeyboardClass *akc = ADB_KEYBOARD_CLASS(oc);
akc->parent_realize = dc->realize;
dc->realize = adb_kbd_realizefn;
device_class_set_parent_realize(dc, adb_kbd_realizefn,
&akc->parent_realize);
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
adc->devreq = adb_kbd_request;

4
hw/input/adb-mouse.c
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@ -228,8 +228,8 @@ static void adb_mouse_class_init(ObjectClass *oc, void *data)
ADBDeviceClass *adc = ADB_DEVICE_CLASS(oc);
ADBMouseClass *amc = ADB_MOUSE_CLASS(oc);
amc->parent_realize = dc->realize;
dc->realize = adb_mouse_realizefn;
device_class_set_parent_realize(dc, adb_mouse_realizefn,
&amc->parent_realize);
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
adc->devreq = adb_mouse_request;

3
hw/intc/arm_gic.c
View File

@ -1461,8 +1461,7 @@ static void arm_gic_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
ARMGICClass *agc = ARM_GIC_CLASS(klass);
agc->parent_realize = dc->realize;
dc->realize = arm_gic_realize;
device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_realize);
}
static const TypeInfo arm_gic_info = {

7
hw/intc/arm_gic_kvm.c
View File

@ -591,10 +591,9 @@ static void kvm_arm_gic_class_init(ObjectClass *klass, void *data)
agcc->pre_save = kvm_arm_gic_get;
agcc->post_load = kvm_arm_gic_put;
kgc->parent_realize = dc->realize;
kgc->parent_reset = dc->reset;
dc->realize = kvm_arm_gic_realize;
dc->reset = kvm_arm_gic_reset;
device_class_set_parent_realize(dc, kvm_arm_gic_realize,
&kgc->parent_realize);
device_class_set_parent_reset(dc, kvm_arm_gic_reset, &kgc->parent_reset);
}
static const TypeInfo kvm_arm_gic_info = {

3
hw/intc/arm_gicv3.c
View File

@ -385,8 +385,7 @@ static void arm_gicv3_class_init(ObjectClass *klass, void *data)
ARMGICv3Class *agc = ARM_GICV3_CLASS(klass);
agcc->post_load = arm_gicv3_post_load;
agc->parent_realize = dc->realize;
dc->realize = arm_gic_realize;
device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_realize);
}
static const TypeInfo arm_gicv3_info = {

3
hw/intc/arm_gicv3_its_kvm.c
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@ -245,11 +245,10 @@ static void kvm_arm_its_class_init(ObjectClass *klass, void *data)
dc->realize = kvm_arm_its_realize;
dc->props = kvm_arm_its_props;
ic->parent_reset = dc->reset;
device_class_set_parent_reset(dc, kvm_arm_its_reset, &ic->parent_reset);
icc->send_msi = kvm_its_send_msi;
icc->pre_save = kvm_arm_its_pre_save;
icc->post_load = kvm_arm_its_post_load;
dc->reset = kvm_arm_its_reset;
}
static const TypeInfo kvm_arm_its_info = {

7
hw/intc/arm_gicv3_kvm.c
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@ -795,10 +795,9 @@ static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data)
agcc->pre_save = kvm_arm_gicv3_get;
agcc->post_load = kvm_arm_gicv3_put;
kgc->parent_realize = dc->realize;
kgc->parent_reset = dc->reset;
dc->realize = kvm_arm_gicv3_realize;
dc->reset = kvm_arm_gicv3_reset;
device_class_set_parent_realize(dc, kvm_arm_gicv3_realize,
&kgc->parent_realize);
device_class_set_parent_reset(dc, kvm_arm_gicv3_reset, &kgc->parent_reset);
}
static const TypeInfo kvm_arm_gicv3_info = {

3
hw/intc/i8259.c
View File

@ -443,8 +443,7 @@ static void i8259_class_init(ObjectClass *klass, void *data)
PICClass *k = PIC_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->parent_realize = dc->realize;
dc->realize = pic_realize;
device_class_set_parent_realize(dc, pic_realize, &k->parent_realize);
dc->reset = pic_reset;
}

4
hw/net/vmxnet3.c
View File

@ -2664,8 +2664,8 @@ static void vmxnet3_class_init(ObjectClass *class, void *data)
c->class_id = PCI_CLASS_NETWORK_ETHERNET;
c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
vc->parent_dc_realize = dc->realize;
dc->realize = vmxnet3_realize;
device_class_set_parent_realize(dc, vmxnet3_realize,
&vc->parent_dc_realize);
dc->desc = "VMWare Paravirtualized Ethernet v3";
dc->reset = vmxnet3_qdev_reset;
dc->vmsd = &vmstate_vmxnet3;

3
hw/pci-bridge/gen_pcie_root_port.c
View File

@ -137,8 +137,7 @@ static void gen_rp_dev_class_init(ObjectClass *klass, void *data)
dc->vmsd = &vmstate_rp_dev;
dc->props = gen_rp_props;
rpc->parent_realize = dc->realize;
dc->realize = gen_rp_realize;
device_class_set_parent_realize(dc, gen_rp_realize, &rpc->parent_realize);
rpc->aer_vector = gen_rp_aer_vector;
rpc->interrupts_init = gen_rp_interrupts_init;

4
hw/scsi/vmw_pvscsi.c
View File

@ -1284,8 +1284,8 @@ static void pvscsi_class_init(ObjectClass *klass, void *data)
k->device_id = PCI_DEVICE_ID_VMWARE_PVSCSI;
k->class_id = PCI_CLASS_STORAGE_SCSI;
k->subsystem_id = 0x1000;
pvs_k->parent_dc_realize = dc->realize;
dc->realize = pvscsi_realize;
device_class_set_parent_realize(dc, pvscsi_realize,
&pvs_k->parent_dc_realize);
dc->reset = pvscsi_reset;
dc->vmsd = &vmstate_pvscsi;
dc->props = pvscsi_properties;

3
hw/timer/i8254.c
View File

@ -358,8 +358,7 @@ static void pit_class_initfn(ObjectClass *klass, void *data)
PITCommonClass *k = PIT_COMMON_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
pc->parent_realize = dc->realize;
dc->realize = pit_realizefn;
device_class_set_parent_realize(dc, pit_realizefn, &pc->parent_realize);
k->set_channel_gate = pit_set_channel_gate;
k->get_channel_info = pit_get_channel_info_common;
k->post_load = pit_post_load;

4
hw/vfio/amd-xgbe.c
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@ -34,8 +34,8 @@ static void vfio_amd_xgbe_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
VFIOAmdXgbeDeviceClass *vcxc =
VFIO_AMD_XGBE_DEVICE_CLASS(klass);
vcxc->parent_realize = dc->realize;
dc->realize = amd_xgbe_realize;
device_class_set_parent_realize(dc, amd_xgbe_realize,
&vcxc->parent_realize);
dc->desc = "VFIO AMD XGBE";
dc->vmsd = &vfio_platform_amd_xgbe_vmstate;
/* Supported by TYPE_VIRT_MACHINE */

4
hw/vfio/calxeda-xgmac.c
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@ -34,8 +34,8 @@ static void vfio_calxeda_xgmac_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
VFIOCalxedaXgmacDeviceClass *vcxc =
VFIO_CALXEDA_XGMAC_DEVICE_CLASS(klass);
vcxc->parent_realize = dc->realize;
dc->realize = calxeda_xgmac_realize;
device_class_set_parent_realize(dc, calxeda_xgmac_realize,
&vcxc->parent_realize);
dc->desc = "VFIO Calxeda XGMAC";
dc->vmsd = &vfio_platform_calxeda_xgmac_vmstate;
/* Supported by TYPE_VIRT_MACHINE */

4
hw/virtio/virtio-pci.c
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@ -1907,8 +1907,8 @@ static void virtio_pci_class_init(ObjectClass *klass, void *data)
k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
k->revision = VIRTIO_PCI_ABI_VERSION;
k->class_id = PCI_CLASS_OTHERS;
vpciklass->parent_dc_realize = dc->realize;
dc->realize = virtio_pci_dc_realize;
device_class_set_parent_realize(dc, virtio_pci_dc_realize,
&vpciklass->parent_dc_realize);
dc->reset = virtio_pci_reset;
}

4
target/alpha/cpu.c
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@ -233,8 +233,8 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
AlphaCPUClass *acc = ALPHA_CPU_CLASS(oc);
acc->parent_realize = dc->realize;
dc->realize = alpha_cpu_realizefn;
device_class_set_parent_realize(dc, alpha_cpu_realizefn,
&acc->parent_realize);
cc->class_by_name = alpha_cpu_class_by_name;
cc->has_work = alpha_cpu_has_work;

4
target/arm/cpu.c
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@ -1722,8 +1722,8 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(acc);
DeviceClass *dc = DEVICE_CLASS(oc);
acc->parent_realize = dc->realize;
dc->realize = arm_cpu_realizefn;
device_class_set_parent_realize(dc, arm_cpu_realizefn,
&acc->parent_realize);
dc->props = arm_cpu_properties;
acc->parent_reset = cc->reset;

4
target/cris/cpu.c
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@ -260,8 +260,8 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->parent_realize = dc->realize;
dc->realize = cris_cpu_realizefn;
device_class_set_parent_realize(dc, cris_cpu_realizefn,
&ccc->parent_realize);
ccc->parent_reset = cc->reset;
cc->reset = cris_cpu_reset;

4
target/hppa/cpu.c
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@ -168,8 +168,8 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
HPPACPUClass *acc = HPPA_CPU_CLASS(oc);
acc->parent_realize = dc->realize;
dc->realize = hppa_cpu_realizefn;
device_class_set_parent_realize(dc, hppa_cpu_realizefn,
&acc->parent_realize);
cc->class_by_name = hppa_cpu_class_by_name;
cc->has_work = hppa_cpu_has_work;

8
target/i386/cpu.c
View File

@ -4705,10 +4705,10 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
DeviceClass *dc = DEVICE_CLASS(oc);
xcc->parent_realize = dc->realize;
xcc->parent_unrealize = dc->unrealize;
dc->realize = x86_cpu_realizefn;
dc->unrealize = x86_cpu_unrealizefn;
device_class_set_parent_realize(dc, x86_cpu_realizefn,
&xcc->parent_realize);
device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
&xcc->parent_unrealize);
dc->props = x86_cpu_properties;
xcc->parent_reset = cc->reset;

5
target/lm32/cpu.c
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@ -236,9 +236,8 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
DeviceClass *dc = DEVICE_CLASS(oc);
lcc->parent_realize = dc->realize;
dc->realize = lm32_cpu_realizefn;
device_class_set_parent_realize(dc, lm32_cpu_realizefn,
&lcc->parent_realize);
lcc->parent_reset = cc->reset;
cc->reset = lm32_cpu_reset;

5
target/m68k/cpu.c
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@ -255,9 +255,8 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
CPUClass *cc = CPU_CLASS(c);
DeviceClass *dc = DEVICE_CLASS(c);
mcc->parent_realize = dc->realize;
dc->realize = m68k_cpu_realizefn;
device_class_set_parent_realize(dc, m68k_cpu_realizefn,
&mcc->parent_realize);
mcc->parent_reset = cc->reset;
cc->reset = m68k_cpu_reset;

5
target/microblaze/cpu.c
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@ -258,9 +258,8 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
mcc->parent_realize = dc->realize;
dc->realize = mb_cpu_realizefn;
device_class_set_parent_realize(dc, mb_cpu_realizefn,
&mcc->parent_realize);
mcc->parent_reset = cc->reset;
cc->reset = mb_cpu_reset;

5
target/mips/cpu.c
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@ -174,9 +174,8 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
CPUClass *cc = CPU_CLASS(c);
DeviceClass *dc = DEVICE_CLASS(c);
mcc->parent_realize = dc->realize;
dc->realize = mips_cpu_realizefn;
device_class_set_parent_realize(dc, mips_cpu_realizefn,
&mcc->parent_realize);
mcc->parent_reset = cc->reset;
cc->reset = mips_cpu_reset;

5
target/moxie/cpu.c
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@ -102,9 +102,8 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
MoxieCPUClass *mcc = MOXIE_CPU_CLASS(oc);
mcc->parent_realize = dc->realize;
dc->realize = moxie_cpu_realizefn;
device_class_set_parent_realize(dc, moxie_cpu_realizefn,
&mcc->parent_realize);
mcc->parent_reset = cc->reset;
cc->reset = moxie_cpu_reset;

4
target/nios2/cpu.c
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@ -187,8 +187,8 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
Nios2CPUClass *ncc = NIOS2_CPU_CLASS(oc);
ncc->parent_realize = dc->realize;
dc->realize = nios2_cpu_realizefn;
device_class_set_parent_realize(dc, nios2_cpu_realizefn,
&ncc->parent_realize);
dc->props = nios2_properties;
ncc->parent_reset = cc->reset;
cc->reset = nios2_cpu_reset;

5
target/openrisc/cpu.c
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@ -132,9 +132,8 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(occ);
DeviceClass *dc = DEVICE_CLASS(oc);
occ->parent_realize = dc->realize;
dc->realize = openrisc_cpu_realizefn;
device_class_set_parent_realize(dc, openrisc_cpu_realizefn,
&occ->parent_realize);
occ->parent_reset = cc->reset;
cc->reset = openrisc_cpu_reset;

8
target/ppc/translate_init.c
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@ -10556,12 +10556,12 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
DeviceClass *dc = DEVICE_CLASS(oc);
pcc->parent_realize = dc->realize;
pcc->parent_unrealize = dc->unrealize;
device_class_set_parent_realize(dc, ppc_cpu_realizefn,
&pcc->parent_realize);
device_class_set_parent_unrealize(dc, ppc_cpu_unrealizefn,
&pcc->parent_unrealize);
pcc->pvr_match = ppc_pvr_match_default;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
dc->realize = ppc_cpu_realizefn;
dc->unrealize = ppc_cpu_unrealizefn;
dc->props = ppc_cpu_properties;
pcc->parent_reset = cc->reset;

4
target/s390x/cpu.c
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@ -464,8 +464,8 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(scc);
DeviceClass *dc = DEVICE_CLASS(oc);
scc->parent_realize = dc->realize;
dc->realize = s390_cpu_realizefn;
device_class_set_parent_realize(dc, s390_cpu_realizefn,
&scc->parent_realize);
dc->props = s390x_cpu_properties;
dc->user_creatable = true;

4
target/sh4/cpu.c
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@ -236,8 +236,8 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
scc->parent_realize = dc->realize;
dc->realize = superh_cpu_realizefn;
device_class_set_parent_realize(dc, superh_cpu_realizefn,
&scc->parent_realize);
scc->parent_reset = cc->reset;
cc->reset = superh_cpu_reset;

4
target/sparc/cpu.c
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@ -858,8 +858,8 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
DeviceClass *dc = DEVICE_CLASS(oc);
scc->parent_realize = dc->realize;
dc->realize = sparc_cpu_realizefn;
device_class_set_parent_realize(dc, sparc_cpu_realizefn,
&scc->parent_realize);
dc->props = sparc_cpu_properties;
scc->parent_reset = cc->reset;

4
target/tilegx/cpu.c
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@ -141,8 +141,8 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
TileGXCPUClass *tcc = TILEGX_CPU_CLASS(oc);
tcc->parent_realize = dc->realize;
dc->realize = tilegx_cpu_realizefn;
device_class_set_parent_realize(dc, tilegx_cpu_realizefn,
&tcc->parent_realize);
tcc->parent_reset = cc->reset;
cc->reset = tilegx_cpu_reset;

4
target/tricore/cpu.c
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@ -153,8 +153,8 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
CPUClass *cc = CPU_CLASS(c);
DeviceClass *dc = DEVICE_CLASS(c);
mcc->parent_realize = dc->realize;
dc->realize = tricore_cpu_realizefn;
device_class_set_parent_realize(dc, tricore_cpu_realizefn,
&mcc->parent_realize);
mcc->parent_reset = cc->reset;
cc->reset = tricore_cpu_reset;

4
target/unicore32/cpu.c
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@ -132,8 +132,8 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
UniCore32CPUClass *ucc = UNICORE32_CPU_CLASS(oc);
ucc->parent_realize = dc->realize;
dc->realize = uc32_cpu_realizefn;
device_class_set_parent_realize(dc, uc32_cpu_realizefn,
&ucc->parent_realize);
cc->class_by_name = uc32_cpu_class_by_name;
cc->has_work = uc32_cpu_has_work;

4
target/xtensa/cpu.c
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@ -151,8 +151,8 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
xcc->parent_realize = dc->realize;
dc->realize = xtensa_cpu_realizefn;
device_class_set_parent_realize(dc, xtensa_cpu_realizefn,
&xcc->parent_realize);
xcc->parent_reset = cc->reset;
cc->reset = xtensa_cpu_reset;