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softfloat: Drop [s]bits{8, 16, 32, 64} types in favor of [u]int{8, 16, 32, 64}_t

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They are defined with the same semantics as the POSIX types,
so prefer those for consistency. Suggested by Peter Maydell.

Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Andreas Färber 2011-03-07 01:34:06 +01:00 committed by Aurelien Jarno
parent 87b8cc3cf3
commit bb98fe42c5
5 changed files with 417 additions and 432 deletions
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182
fpu/softfloat-macros.h
View File

@ -44,9 +44,9 @@ these four paragraphs for those parts of this code that are retained.
| The result is stored in the location pointed to by `zPtr'.
*----------------------------------------------------------------------------*/
INLINE void shift32RightJamming( bits32 a, int16 count, bits32 *zPtr )
INLINE void shift32RightJamming( uint32_t a, int16 count, uint32_t *zPtr )
{
bits32 z;
uint32_t z;
if ( count == 0 ) {
z = a;
@ -70,9 +70,9 @@ INLINE void shift32RightJamming( bits32 a, int16 count, bits32 *zPtr )
| The result is stored in the location pointed to by `zPtr'.
*----------------------------------------------------------------------------*/
INLINE void shift64RightJamming( bits64 a, int16 count, bits64 *zPtr )
INLINE void shift64RightJamming( uint64_t a, int16 count, uint64_t *zPtr )
{
bits64 z;
uint64_t z;
if ( count == 0 ) {
z = a;
@ -106,9 +106,9 @@ INLINE void shift64RightJamming( bits64 a, int16 count, bits64 *zPtr )
INLINE void
shift64ExtraRightJamming(
bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )
uint64_t a0, uint64_t a1, int16 count, uint64_t *z0Ptr, uint64_t *z1Ptr )
{
bits64 z0, z1;
uint64_t z0, z1;
int8 negCount = ( - count ) & 63;
if ( count == 0 ) {
@ -143,9 +143,9 @@ INLINE void
INLINE void
shift128Right(
bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )
uint64_t a0, uint64_t a1, int16 count, uint64_t *z0Ptr, uint64_t *z1Ptr )
{
bits64 z0, z1;
uint64_t z0, z1;
int8 negCount = ( - count ) & 63;
if ( count == 0 ) {
@ -178,9 +178,9 @@ INLINE void
INLINE void
shift128RightJamming(
bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )
uint64_t a0, uint64_t a1, int16 count, uint64_t *z0Ptr, uint64_t *z1Ptr )
{
bits64 z0, z1;
uint64_t z0, z1;
int8 negCount = ( - count ) & 63;
if ( count == 0 ) {
@ -229,16 +229,16 @@ INLINE void
INLINE void
shift128ExtraRightJamming(
bits64 a0,
bits64 a1,
bits64 a2,
uint64_t a0,
uint64_t a1,
uint64_t a2,
int16 count,
bits64 *z0Ptr,
bits64 *z1Ptr,
bits64 *z2Ptr
uint64_t *z0Ptr,
uint64_t *z1Ptr,
uint64_t *z2Ptr
)
{
bits64 z0, z1, z2;
uint64_t z0, z1, z2;
int8 negCount = ( - count ) & 63;
if ( count == 0 ) {
@ -287,7 +287,7 @@ INLINE void
INLINE void
shortShift128Left(
bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )
uint64_t a0, uint64_t a1, int16 count, uint64_t *z0Ptr, uint64_t *z1Ptr )
{
*z1Ptr = a1<<count;
@ -306,16 +306,16 @@ INLINE void
INLINE void
shortShift192Left(
bits64 a0,
bits64 a1,
bits64 a2,
uint64_t a0,
uint64_t a1,
uint64_t a2,
int16 count,
bits64 *z0Ptr,
bits64 *z1Ptr,
bits64 *z2Ptr
uint64_t *z0Ptr,
uint64_t *z1Ptr,
uint64_t *z2Ptr
)
{
bits64 z0, z1, z2;
uint64_t z0, z1, z2;
int8 negCount;
z2 = a2<<count;
@ -341,9 +341,9 @@ INLINE void
INLINE void
add128(
bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 *z0Ptr, bits64 *z1Ptr )
uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1, uint64_t *z0Ptr, uint64_t *z1Ptr )
{
bits64 z1;
uint64_t z1;
z1 = a1 + b1;
*z1Ptr = z1;
@ -361,18 +361,18 @@ INLINE void
INLINE void
add192(
bits64 a0,
bits64 a1,
bits64 a2,
bits64 b0,
bits64 b1,
bits64 b2,
bits64 *z0Ptr,
bits64 *z1Ptr,
bits64 *z2Ptr
uint64_t a0,
uint64_t a1,
uint64_t a2,
uint64_t b0,
uint64_t b1,
uint64_t b2,
uint64_t *z0Ptr,
uint64_t *z1Ptr,
uint64_t *z2Ptr
)
{
bits64 z0, z1, z2;
uint64_t z0, z1, z2;
int8 carry0, carry1;
z2 = a2 + b2;
@ -399,7 +399,7 @@ INLINE void
INLINE void
sub128(
bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 *z0Ptr, bits64 *z1Ptr )
uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1, uint64_t *z0Ptr, uint64_t *z1Ptr )
{
*z1Ptr = a1 - b1;
@ -417,18 +417,18 @@ INLINE void
INLINE void
sub192(
bits64 a0,
bits64 a1,
bits64 a2,
bits64 b0,
bits64 b1,
bits64 b2,
bits64 *z0Ptr,
bits64 *z1Ptr,
bits64 *z2Ptr
uint64_t a0,
uint64_t a1,
uint64_t a2,
uint64_t b0,
uint64_t b1,
uint64_t b2,
uint64_t *z0Ptr,
uint64_t *z1Ptr,
uint64_t *z2Ptr
)
{
bits64 z0, z1, z2;
uint64_t z0, z1, z2;
int8 borrow0, borrow1;
z2 = a2 - b2;
@ -451,21 +451,21 @@ INLINE void
| `z0Ptr' and `z1Ptr'.
*----------------------------------------------------------------------------*/
INLINE void mul64To128( bits64 a, bits64 b, bits64 *z0Ptr, bits64 *z1Ptr )
INLINE void mul64To128( uint64_t a, uint64_t b, uint64_t *z0Ptr, uint64_t *z1Ptr )
{
bits32 aHigh, aLow, bHigh, bLow;
bits64 z0, zMiddleA, zMiddleB, z1;
uint32_t aHigh, aLow, bHigh, bLow;
uint64_t z0, zMiddleA, zMiddleB, z1;
aLow = a;
aHigh = a>>32;
bLow = b;
bHigh = b>>32;
z1 = ( (bits64) aLow ) * bLow;
zMiddleA = ( (bits64) aLow ) * bHigh;
zMiddleB = ( (bits64) aHigh ) * bLow;
z0 = ( (bits64) aHigh ) * bHigh;
z1 = ( (uint64_t) aLow ) * bLow;
zMiddleA = ( (uint64_t) aLow ) * bHigh;
zMiddleB = ( (uint64_t) aHigh ) * bLow;
z0 = ( (uint64_t) aHigh ) * bHigh;
zMiddleA += zMiddleB;
z0 += ( ( (bits64) ( zMiddleA < zMiddleB ) )<<32 ) + ( zMiddleA>>32 );
z0 += ( ( (uint64_t) ( zMiddleA < zMiddleB ) )<<32 ) + ( zMiddleA>>32 );
zMiddleA <<= 32;
z1 += zMiddleA;
z0 += ( z1 < zMiddleA );
@ -483,15 +483,15 @@ INLINE void mul64To128( bits64 a, bits64 b, bits64 *z0Ptr, bits64 *z1Ptr )
INLINE void
mul128By64To192(
bits64 a0,
bits64 a1,
bits64 b,
bits64 *z0Ptr,
bits64 *z1Ptr,
bits64 *z2Ptr
uint64_t a0,
uint64_t a1,
uint64_t b,
uint64_t *z0Ptr,
uint64_t *z1Ptr,
uint64_t *z2Ptr
)
{
bits64 z0, z1, z2, more1;
uint64_t z0, z1, z2, more1;
mul64To128( a1, b, &z1, &z2 );
mul64To128( a0, b, &z0, &more1 );
@ -511,18 +511,18 @@ INLINE void
INLINE void
mul128To256(
bits64 a0,
bits64 a1,
bits64 b0,
bits64 b1,
bits64 *z0Ptr,
bits64 *z1Ptr,
bits64 *z2Ptr,
bits64 *z3Ptr
uint64_t a0,
uint64_t a1,
uint64_t b0,
uint64_t b1,
uint64_t *z0Ptr,
uint64_t *z1Ptr,
uint64_t *z2Ptr,
uint64_t *z3Ptr
)
{
bits64 z0, z1, z2, z3;
bits64 more1, more2;
uint64_t z0, z1, z2, z3;
uint64_t more1, more2;
mul64To128( a1, b1, &z2, &z3 );
mul64To128( a1, b0, &z1, &more2 );
@ -548,18 +548,18 @@ INLINE void
| unsigned integer is returned.
*----------------------------------------------------------------------------*/
static bits64 estimateDiv128To64( bits64 a0, bits64 a1, bits64 b )
static uint64_t estimateDiv128To64( uint64_t a0, uint64_t a1, uint64_t b )
{
bits64 b0, b1;
bits64 rem0, rem1, term0, term1;
bits64 z;
uint64_t b0, b1;
uint64_t rem0, rem1, term0, term1;
uint64_t z;
if ( b <= a0 ) return LIT64( 0xFFFFFFFFFFFFFFFF );
b0 = b>>32;
z = ( b0<<32 <= a0 ) ? LIT64( 0xFFFFFFFF00000000 ) : ( a0 / b0 )<<32;
mul64To128( b, z, &term0, &term1 );
sub128( a0, a1, term0, term1, &rem0, &rem1 );
while ( ( (sbits64) rem0 ) < 0 ) {
while ( ( (int64_t) rem0 ) < 0 ) {
z -= LIT64( 0x100000000 );
b1 = b<<32;
add128( rem0, rem1, b0, b1, &rem0, &rem1 );
@ -580,18 +580,18 @@ static bits64 estimateDiv128To64( bits64 a0, bits64 a1, bits64 b )
| value.
*----------------------------------------------------------------------------*/
static bits32 estimateSqrt32( int16 aExp, bits32 a )
static uint32_t estimateSqrt32( int16 aExp, uint32_t a )
{
static const bits16 sqrtOddAdjustments[] = {
static const uint16_t sqrtOddAdjustments[] = {
0x0004, 0x0022, 0x005D, 0x00B1, 0x011D, 0x019F, 0x0236, 0x02E0,
0x039C, 0x0468, 0x0545, 0x0631, 0x072B, 0x0832, 0x0946, 0x0A67
};
static const bits16 sqrtEvenAdjustments[] = {
static const uint16_t sqrtEvenAdjustments[] = {
0x0A2D, 0x08AF, 0x075A, 0x0629, 0x051A, 0x0429, 0x0356, 0x029E,
0x0200, 0x0179, 0x0109, 0x00AF, 0x0068, 0x0034, 0x0012, 0x0002
};
int8 index;
bits32 z;
uint32_t z;
index = ( a>>27 ) & 15;
if ( aExp & 1 ) {
@ -603,9 +603,9 @@ static bits32 estimateSqrt32( int16 aExp, bits32 a )
z = 0x8000 + ( a>>17 ) - sqrtEvenAdjustments[ (int)index ];
z = a / z + z;
z = ( 0x20000 <= z ) ? 0xFFFF8000 : ( z<<15 );
if ( z <= a ) return (bits32) ( ( (sbits32) a )>>1 );
if ( z <= a ) return (uint32_t) ( ( (int32_t) a )>>1 );
}
return ( (bits32) ( ( ( (bits64) a )<<31 ) / z ) ) + ( z>>1 );
return ( (uint32_t) ( ( ( (uint64_t) a )<<31 ) / z ) ) + ( z>>1 );
}
@ -614,7 +614,7 @@ static bits32 estimateSqrt32( int16 aExp, bits32 a )
| `a'. If `a' is zero, 32 is returned.
*----------------------------------------------------------------------------*/
static int8 countLeadingZeros32( bits32 a )
static int8 countLeadingZeros32( uint32_t a )
{
static const int8 countLeadingZerosHigh[] = {
8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4,
@ -655,12 +655,12 @@ static int8 countLeadingZeros32( bits32 a )
| `a'. If `a' is zero, 64 is returned.
*----------------------------------------------------------------------------*/
static int8 countLeadingZeros64( bits64 a )
static int8 countLeadingZeros64( uint64_t a )
{
int8 shiftCount;
shiftCount = 0;
if ( a < ( (bits64) 1 )<<32 ) {
if ( a < ( (uint64_t) 1 )<<32 ) {
shiftCount += 32;
}
else {
@ -677,7 +677,7 @@ static int8 countLeadingZeros64( bits64 a )
| Otherwise, returns 0.
*----------------------------------------------------------------------------*/
INLINE flag eq128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )
INLINE flag eq128( uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1 )
{
return ( a0 == b0 ) && ( a1 == b1 );
@ -690,7 +690,7 @@ INLINE flag eq128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )
| Otherwise, returns 0.
*----------------------------------------------------------------------------*/
INLINE flag le128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )
INLINE flag le128( uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1 )
{
return ( a0 < b0 ) || ( ( a0 == b0 ) && ( a1 <= b1 ) );
@ -703,7 +703,7 @@ INLINE flag le128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )
| returns 0.
*----------------------------------------------------------------------------*/
INLINE flag lt128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )
INLINE flag lt128( uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1 )
{
return ( a0 < b0 ) || ( ( a0 == b0 ) && ( a1 < b1 ) );
@ -716,7 +716,7 @@ INLINE flag lt128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )
| Otherwise, returns 0.
*----------------------------------------------------------------------------*/
INLINE flag ne128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )
INLINE flag ne128( uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1 )
{
return ( a0 != b0 ) || ( a1 != b1 );

6
fpu/softfloat-native.c
View File

@ -418,7 +418,7 @@ int float64_is_quiet_nan( float64 a1 )
u.f = a1;
a = u.i;
return ( LIT64( 0xFFF0000000000000 ) < (bits64) ( a<<1 ) );
return ( LIT64( 0xFFF0000000000000 ) < (uint64_t) ( a<<1 ) );
}
@ -500,7 +500,7 @@ int floatx80_is_signaling_nan( floatx80 a1)
aLow = u.i.low & ~ LIT64( 0x4000000000000000 );
return
( ( u.i.high & 0x7FFF ) == 0x7FFF )
&& (bits64) ( aLow<<1 )
&& (uint64_t) ( aLow<<1 )
&& ( u.i.low == aLow );
}
@ -508,7 +508,7 @@ int floatx80_is_quiet_nan( floatx80 a1 )
{
floatx80u u;
u.f = a1;
return ( ( u.i.high & 0x7FFF ) == 0x7FFF ) && (bits64) ( u.i.low<<1 );
return ( ( u.i.high & 0x7FFF ) == 0x7FFF ) && (uint64_t) ( u.i.low<<1 );
}
#endif

62
fpu/softfloat-specialize.h
View File

@ -52,7 +52,7 @@ void float_raise( int8 flags STATUS_PARAM )
*----------------------------------------------------------------------------*/
typedef struct {
flag sign;
bits64 high, low;
uint64_t high, low;
} commonNaNT;
/*----------------------------------------------------------------------------
@ -120,7 +120,7 @@ static commonNaNT float16ToCommonNaN( float16 a STATUS_PARAM )
if ( float16_is_signaling_nan( a ) ) float_raise( float_flag_invalid STATUS_VAR );
z.sign = float16_val(a) >> 15;
z.low = 0;
z.high = ((bits64) float16_val(a))<<54;
z.high = ((uint64_t) float16_val(a))<<54;
return z;
}
@ -156,7 +156,7 @@ int float32_is_quiet_nan( float32 a_ )
#if SNAN_BIT_IS_ONE
return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF );
#else
return ( 0xFF800000 <= (bits32) ( a<<1 ) );
return ( 0xFF800000 <= (uint32_t) ( a<<1 ) );
#endif
}
@ -169,7 +169,7 @@ int float32_is_signaling_nan( float32 a_ )
{
uint32_t a = float32_val(a_);
#if SNAN_BIT_IS_ONE
return ( 0xFF800000 <= (bits32) ( a<<1 ) );
return ( 0xFF800000 <= (uint32_t) ( a<<1 ) );
#else
return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF );
#endif
@ -190,7 +190,7 @@ float32 float32_maybe_silence_nan( float32 a_ )
# error Rules for silencing a signaling NaN are target-specific
# endif
#else
bits32 a = float32_val(a_);
uint32_t a = float32_val(a_);
a |= (1 << 22);
return make_float32(a);
#endif
@ -211,7 +211,7 @@ static commonNaNT float32ToCommonNaN( float32 a STATUS_PARAM )
if ( float32_is_signaling_nan( a ) ) float_raise( float_flag_invalid STATUS_VAR );
z.sign = float32_val(a)>>31;
z.low = 0;
z.high = ( (bits64) float32_val(a) )<<41;
z.high = ( (uint64_t) float32_val(a) )<<41;
return z;
}
@ -222,7 +222,7 @@ static commonNaNT float32ToCommonNaN( float32 a STATUS_PARAM )
static float32 commonNaNToFloat32( commonNaNT a STATUS_PARAM)
{
bits32 mantissa = a.high>>41;
uint32_t mantissa = a.high>>41;
if ( STATUS(default_nan_mode) ) {
return float32_default_nan;
@ -230,7 +230,7 @@ static float32 commonNaNToFloat32( commonNaNT a STATUS_PARAM)
if ( mantissa )
return make_float32(
( ( (bits32) a.sign )<<31 ) | 0x7F800000 | ( a.high>>41 ) );
( ( (uint32_t) a.sign )<<31 ) | 0x7F800000 | ( a.high>>41 ) );
else
return float32_default_nan;
}
@ -357,7 +357,7 @@ static float32 propagateFloat32NaN( float32 a, float32 b STATUS_PARAM)
{
flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
flag aIsLargerSignificand;
bits32 av, bv;
uint32_t av, bv;
aIsQuietNaN = float32_is_quiet_nan( a );
aIsSignalingNaN = float32_is_signaling_nan( a );
@ -371,9 +371,9 @@ static float32 propagateFloat32NaN( float32 a, float32 b STATUS_PARAM)
if ( STATUS(default_nan_mode) )
return float32_default_nan;
if ((bits32)(av<<1) < (bits32)(bv<<1)) {
if ((uint32_t)(av<<1) < (uint32_t)(bv<<1)) {
aIsLargerSignificand = 0;
} else if ((bits32)(bv<<1) < (bits32)(av<<1)) {
} else if ((uint32_t)(bv<<1) < (uint32_t)(av<<1)) {
aIsLargerSignificand = 1;
} else {
aIsLargerSignificand = (av < bv) ? 1 : 0;
@ -394,13 +394,13 @@ static float32 propagateFloat32NaN( float32 a, float32 b STATUS_PARAM)
int float64_is_quiet_nan( float64 a_ )
{
bits64 a = float64_val(a_);
uint64_t a = float64_val(a_);
#if SNAN_BIT_IS_ONE
return
( ( ( a>>51 ) & 0xFFF ) == 0xFFE )
&& ( a & LIT64( 0x0007FFFFFFFFFFFF ) );
#else
return ( LIT64( 0xFFF0000000000000 ) <= (bits64) ( a<<1 ) );
return ( LIT64( 0xFFF0000000000000 ) <= (uint64_t) ( a<<1 ) );
#endif
}
@ -411,9 +411,9 @@ int float64_is_quiet_nan( float64 a_ )
int float64_is_signaling_nan( float64 a_ )
{
bits64 a = float64_val(a_);
uint64_t a = float64_val(a_);
#if SNAN_BIT_IS_ONE
return ( LIT64( 0xFFF0000000000000 ) <= (bits64) ( a<<1 ) );
return ( LIT64( 0xFFF0000000000000 ) <= (uint64_t) ( a<<1 ) );
#else
return
( ( ( a>>51 ) & 0xFFF ) == 0xFFE )
@ -436,7 +436,7 @@ float64 float64_maybe_silence_nan( float64 a_ )
# error Rules for silencing a signaling NaN are target-specific
# endif
#else
bits64 a = float64_val(a_);
uint64_t a = float64_val(a_);
a |= LIT64( 0x0008000000000000 );
return make_float64(a);
#endif
@ -468,7 +468,7 @@ static commonNaNT float64ToCommonNaN( float64 a STATUS_PARAM)
static float64 commonNaNToFloat64( commonNaNT a STATUS_PARAM)
{
bits64 mantissa = a.high>>12;
uint64_t mantissa = a.high>>12;
if ( STATUS(default_nan_mode) ) {
return float64_default_nan;
@ -476,7 +476,7 @@ static float64 commonNaNToFloat64( commonNaNT a STATUS_PARAM)
if ( mantissa )
return make_float64(
( ( (bits64) a.sign )<<63 )
( ( (uint64_t) a.sign )<<63 )
| LIT64( 0x7FF0000000000000 )
| ( a.high>>12 ));
else
@ -493,7 +493,7 @@ static float64 propagateFloat64NaN( float64 a, float64 b STATUS_PARAM)
{
flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
flag aIsLargerSignificand;
bits64 av, bv;
uint64_t av, bv;
aIsQuietNaN = float64_is_quiet_nan( a );
aIsSignalingNaN = float64_is_signaling_nan( a );
@ -507,9 +507,9 @@ static float64 propagateFloat64NaN( float64 a, float64 b STATUS_PARAM)
if ( STATUS(default_nan_mode) )
return float64_default_nan;
if ((bits64)(av<<1) < (bits64)(bv<<1)) {
if ((uint64_t)(av<<1) < (uint64_t)(bv<<1)) {
aIsLargerSignificand = 0;
} else if ((bits64)(bv<<1) < (bits64)(av<<1)) {
} else if ((uint64_t)(bv<<1) < (uint64_t)(av<<1)) {
aIsLargerSignificand = 1;
} else {
aIsLargerSignificand = (av < bv) ? 1 : 0;
@ -534,16 +534,16 @@ static float64 propagateFloat64NaN( float64 a, float64 b STATUS_PARAM)
int floatx80_is_quiet_nan( floatx80 a )
{
#if SNAN_BIT_IS_ONE
bits64 aLow;
uint64_t aLow;
aLow = a.low & ~ LIT64( 0x4000000000000000 );
return
( ( a.high & 0x7FFF ) == 0x7FFF )
&& (bits64) ( aLow<<1 )
&& (uint64_t) ( aLow<<1 )
&& ( a.low == aLow );
#else
return ( ( a.high & 0x7FFF ) == 0x7FFF )
&& (LIT64( 0x8000000000000000 ) <= ((bits64) ( a.low<<1 )));
&& (LIT64( 0x8000000000000000 ) <= ((uint64_t) ( a.low<<1 )));
#endif
}
@ -557,14 +557,14 @@ int floatx80_is_signaling_nan( floatx80 a )
{
#if SNAN_BIT_IS_ONE
return ( ( a.high & 0x7FFF ) == 0x7FFF )
&& (LIT64( 0x8000000000000000 ) <= ((bits64) ( a.low<<1 )));
&& (LIT64( 0x8000000000000000 ) <= ((uint64_t) ( a.low<<1 )));
#else
bits64 aLow;
uint64_t aLow;
aLow = a.low & ~ LIT64( 0x4000000000000000 );
return
( ( a.high & 0x7FFF ) == 0x7FFF )
&& (bits64) ( aLow<<1 )
&& (uint64_t) ( aLow<<1 )
&& ( a.low == aLow );
#endif
}
@ -628,7 +628,7 @@ static floatx80 commonNaNToFloatx80( commonNaNT a STATUS_PARAM)
z.low = a.high;
else
z.low = floatx80_default_nan_low;
z.high = ( ( (bits16) a.sign )<<15 ) | 0x7FFF;
z.high = ( ( (uint16_t) a.sign )<<15 ) | 0x7FFF;
return z;
}
@ -689,7 +689,7 @@ int float128_is_quiet_nan( float128 a )
&& ( a.low || ( a.high & LIT64( 0x00007FFFFFFFFFFF ) ) );
#else
return
( LIT64( 0xFFFE000000000000 ) <= (bits64) ( a.high<<1 ) )
( LIT64( 0xFFFE000000000000 ) <= (uint64_t) ( a.high<<1 ) )
&& ( a.low || ( a.high & LIT64( 0x0000FFFFFFFFFFFF ) ) );
#endif
}
@ -703,7 +703,7 @@ int float128_is_signaling_nan( float128 a )
{
#if SNAN_BIT_IS_ONE
return
( LIT64( 0xFFFE000000000000 ) <= (bits64) ( a.high<<1 ) )
( LIT64( 0xFFFE000000000000 ) <= (uint64_t) ( a.high<<1 ) )
&& ( a.low || ( a.high & LIT64( 0x0000FFFFFFFFFFFF ) ) );
#else
return
@ -767,7 +767,7 @@ static float128 commonNaNToFloat128( commonNaNT a STATUS_PARAM)
}
shift128Right( a.high, a.low, 16, &z.high, &z.low );
z.high |= ( ( (bits64) a.sign )<<63 ) | LIT64( 0x7FFF000000000000 );
z.high |= ( ( (uint64_t) a.sign )<<63 ) | LIT64( 0x7FFF000000000000 );
return z;
}

584
fpu/softfloat.c
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File diff suppressed because it is too large Load Diff

15
fpu/softfloat.h
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@ -65,21 +65,6 @@ typedef signed int int32;
typedef uint64_t uint64;
typedef int64_t int64;
/*----------------------------------------------------------------------------
| Each of the following `typedef's defines a type that holds integers
| of _exactly_ the number of bits specified. For instance, for most
| implementation of C, `bits16' and `sbits16' should be `typedef'ed to
| `unsigned short int' and `signed short int' (or `short int'), respectively.
*----------------------------------------------------------------------------*/
typedef uint8_t bits8;
typedef int8_t sbits8;
typedef uint16_t bits16;
typedef int16_t sbits16;
typedef uint32_t bits32;
typedef int32_t sbits32;
typedef uint64_t bits64;
typedef int64_t sbits64;
#define LIT64( a ) a##LL
#define INLINE static inline