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target/openrisc: Make VR and PPC read-only

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These SPRs are read-only.  The writes can simply be ignored,
as we already do for other read-only (or missing) registers.
There is no reason to mask the value in env->vr.

Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2019-08-25 14:28:37 -07:00
parent d29f4368a7
commit b72e3ff658
2 changed files with 1 additions and 12 deletions
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3
target/openrisc/cpu.h
View File

@ -68,9 +68,6 @@ enum {
(reg) |= ((v & 0x1f) << 2);\
} while (0)
/* Version Register */
#define SPR_VR 0xFFFF003F
/* Interrupt */
#define NR_IRQS 32

10
target/openrisc/sys_helper.c
View File

@ -39,10 +39,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
int idx;
switch (spr) {
case TO_SPR(0, 0): /* VR */
env->vr = rb;
break;
case TO_SPR(0, 11): /* EVBAR */
env->evbar = rb;
break;
@ -62,10 +58,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
cpu_set_sr(env, rb);
break;
case TO_SPR(0, 18): /* PPC */
env->ppc = rb;
break;
case TO_SPR(0, 32): /* EPCR */
env->epcr = rb;
break;
@ -204,7 +196,7 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
switch (spr) {
case TO_SPR(0, 0): /* VR */
return env->vr & SPR_VR;
return env->vr;
case TO_SPR(0, 1): /* UPR */
return env->upr; /* TT, DM, IM, UP present */