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target-mips: add SELEQZ and SELNEZ instructions

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Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
This commit is contained in:
Leon Alrae 2014-06-27 08:49:01 +01:00
parent fecd264695
commit b691d9d2a0
2 changed files with 24 additions and 2 deletions
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8
disas/mips.c
View File

@ -521,6 +521,8 @@ struct mips_opcode
#define INSN_ISA64 0x00000040
#define INSN_ISA32R2 0x00000080
#define INSN_ISA64R2 0x00000100
#define INSN_ISA32R6 0x00000200
#define INSN_ISA64R6 0x00000400
/* Masks used for MIPS-defined ASEs. */
#define INSN_ASE_MASK 0x0000f000
@ -585,6 +587,8 @@ struct mips_opcode
#define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2)
#define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
#define ISA_MIPS32R6 (ISA_MIPS32R2 | INSN_ISA32R6)
#define ISA_MIPS64R6 (ISA_MIPS64R2 | INSN_ISA32R6 | INSN_ISA64R6)
/* CPU defines, use instead of hardcoding processor number. Keep this
in sync with bfd/archures.c in order for machine selection to work. */
@ -1121,6 +1125,8 @@ extern const int bfd_mips16_num_opcodes;
#define I64 INSN_ISA64
#define I33 INSN_ISA32R2
#define I65 INSN_ISA64R2
#define I32R6 INSN_ISA32R6
#define I64R6 INSN_ISA64R6
/* MIPS64 MIPS-3D ASE support. */
#define I16 INSN_MIPS16
@ -1209,6 +1215,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
them first. The assemblers uses a hash table based on the
instruction name anyhow. */
/* name, args, match, mask, pinfo, membership */
{"seleqz", "d,v,t", 0x00000035, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
{"selnez", "d,v,t", 0x00000037, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4|I32|G3 },
{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, 0, I4|I33 },
{"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */

18
target-mips/translate.c
View File

@ -193,6 +193,9 @@ enum {
OPC_MOVZ = 0x0A | OPC_SPECIAL,
OPC_MOVN = 0x0B | OPC_SPECIAL,
OPC_SELEQZ = 0x35 | OPC_SPECIAL,
OPC_SELNEZ = 0x37 | OPC_SPECIAL,
OPC_MOVCI = 0x01 | OPC_SPECIAL,
/* Special */
@ -205,8 +208,6 @@ enum {
OPC_SPECIAL15_RESERVED = 0x15 | OPC_SPECIAL,
OPC_SPECIAL28_RESERVED = 0x28 | OPC_SPECIAL,
OPC_SPECIAL29_RESERVED = 0x29 | OPC_SPECIAL,
OPC_SPECIAL35_RESERVED = 0x35 | OPC_SPECIAL,
OPC_SPECIAL37_RESERVED = 0x37 | OPC_SPECIAL,
OPC_SPECIAL39_RESERVED = 0x39 | OPC_SPECIAL,
OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL,
};
@ -2412,6 +2413,14 @@ static void gen_cond_move(DisasContext *ctx, uint32_t opc,
tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]);
opn = "movz";
break;
case OPC_SELNEZ:
tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, t1);
opn = "selnez";
break;
case OPC_SELEQZ:
tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, t1);
opn = "seleqz";
break;
}
tcg_temp_free(t2);
tcg_temp_free(t1);
@ -14533,6 +14542,11 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
INSN_LOONGSON2E | INSN_LOONGSON2F);
gen_cond_move(ctx, op1, rd, rs, rt);
break;
case OPC_SELEQZ:
case OPC_SELNEZ:
check_insn(ctx, ISA_MIPS32R6);
gen_cond_move(ctx, op1, rd, rs, rt);
break;
case OPC_ADD ... OPC_SUBU:
gen_arith(ctx, op1, rd, rs, rt);
break;