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target/i386: Fix 32-bit wrapping of pc/eip computation
In 32-bit mode, pc = eip + cs_base is also 32-bit, and must wrap.
Failure to do so results in incorrect memory exceptions to the guest.
Before 732d548732
, this was implicitly done via truncation to
target_ulong but only in qemu-system-i386, not qemu-system-x86_64.
To fix this, we must add conditional zero-extensions.
Since we have to test for 32 vs 64-bit anyway, note that cs_base
is always zero in 64-bit mode.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2022
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20231212172510.103305-1-richard.henderson@linaro.org>
This commit is contained in:
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9c74490bff
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@ -2324,10 +2324,15 @@ static inline int cpu_mmu_index_kernel(CPUX86State *env)
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static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc,
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uint64_t *cs_base, uint32_t *flags)
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{
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*cs_base = env->segs[R_CS].base;
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*pc = *cs_base + env->eip;
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*flags = env->hflags |
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(env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
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if (env->hflags & HF_CS64_MASK) {
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*cs_base = 0;
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*pc = env->eip;
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} else {
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*cs_base = env->segs[R_CS].base;
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*pc = (uint32_t)(*cs_base + env->eip);
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}
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}
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void do_cpu_init(X86CPU *cpu);
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@ -52,7 +52,12 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs,
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/* The instruction pointer is always up to date with CF_PCREL. */
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if (!(tb_cflags(tb) & CF_PCREL)) {
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CPUX86State *env = cpu_env(cs);
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env->eip = tb->pc - tb->cs_base;
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if (tb->flags & HF_CS64_MASK) {
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env->eip = tb->pc;
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} else {
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env->eip = (uint32_t)(tb->pc - tb->cs_base);
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}
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}
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}
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@ -66,8 +71,10 @@ static void x86_restore_state_to_opc(CPUState *cs,
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if (tb_cflags(tb) & CF_PCREL) {
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env->eip = (env->eip & TARGET_PAGE_MASK) | data[0];
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} else if (tb->flags & HF_CS64_MASK) {
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env->eip = data[0];
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} else {
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env->eip = data[0] - tb->cs_base;
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env->eip = (uint32_t)(data[0] - tb->cs_base);
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}
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if (cc_op != CC_OP_DYNAMIC) {
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env->cc_op = cc_op;
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@ -552,8 +552,10 @@ static void gen_update_eip_cur(DisasContext *s)
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assert(s->pc_save != -1);
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if (tb_cflags(s->base.tb) & CF_PCREL) {
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tcg_gen_addi_tl(cpu_eip, cpu_eip, s->base.pc_next - s->pc_save);
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} else if (CODE64(s)) {
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tcg_gen_movi_tl(cpu_eip, s->base.pc_next);
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} else {
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tcg_gen_movi_tl(cpu_eip, s->base.pc_next - s->cs_base);
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tcg_gen_movi_tl(cpu_eip, (uint32_t)(s->base.pc_next - s->cs_base));
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}
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s->pc_save = s->base.pc_next;
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}
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@ -563,8 +565,10 @@ static void gen_update_eip_next(DisasContext *s)
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assert(s->pc_save != -1);
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if (tb_cflags(s->base.tb) & CF_PCREL) {
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tcg_gen_addi_tl(cpu_eip, cpu_eip, s->pc - s->pc_save);
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} else if (CODE64(s)) {
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tcg_gen_movi_tl(cpu_eip, s->base.pc_next);
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} else {
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tcg_gen_movi_tl(cpu_eip, s->pc - s->cs_base);
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tcg_gen_movi_tl(cpu_eip, (uint32_t)(s->base.pc_next - s->cs_base));
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}
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s->pc_save = s->pc;
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}
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@ -610,8 +614,10 @@ static TCGv eip_next_tl(DisasContext *s)
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TCGv ret = tcg_temp_new();
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tcg_gen_addi_tl(ret, cpu_eip, s->pc - s->pc_save);
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return ret;
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} else if (CODE64(s)) {
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return tcg_constant_tl(s->pc);
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} else {
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return tcg_constant_tl(s->pc - s->cs_base);
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return tcg_constant_tl((uint32_t)(s->pc - s->cs_base));
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}
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}
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@ -622,8 +628,10 @@ static TCGv eip_cur_tl(DisasContext *s)
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TCGv ret = tcg_temp_new();
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tcg_gen_addi_tl(ret, cpu_eip, s->base.pc_next - s->pc_save);
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return ret;
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} else if (CODE64(s)) {
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return tcg_constant_tl(s->base.pc_next);
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} else {
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return tcg_constant_tl(s->base.pc_next - s->cs_base);
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return tcg_constant_tl((uint32_t)(s->base.pc_next - s->cs_base));
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}
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}
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@ -2837,6 +2845,10 @@ static void gen_jmp_rel(DisasContext *s, MemOp ot, int diff, int tb_num)
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}
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}
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new_eip &= mask;
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new_pc = new_eip + s->cs_base;
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if (!CODE64(s)) {
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new_pc = (uint32_t)new_pc;
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}
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gen_update_cc_op(s);
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set_cc_op(s, CC_OP_DYNAMIC);
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@ -2854,8 +2866,7 @@ static void gen_jmp_rel(DisasContext *s, MemOp ot, int diff, int tb_num)
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}
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}
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if (use_goto_tb &&
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translator_use_goto_tb(&s->base, new_eip + s->cs_base)) {
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if (use_goto_tb && translator_use_goto_tb(&s->base, new_pc)) {
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/* jump to same page: we can use a direct jump */
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tcg_gen_goto_tb(tb_num);
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if (!(tb_cflags(s->base.tb) & CF_PCREL)) {
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