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target-mips: fix broken snapshotting
Recently added CP0.BadInstr and CP0.BadInstrP registers ended up in cpu_load() under different offset than in cpu_save(). These and all registers between were incorrectly restored. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
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@ -285,6 +285,10 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
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qemu_get_sbe32s(f, &env->CP0_SRSConf4);
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qemu_get_sbe32s(f, &env->CP0_HWREna);
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qemu_get_betls(f, &env->CP0_BadVAddr);
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if (version_id >= 5) {
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qemu_get_be32s(f, &env->CP0_BadInstr);
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qemu_get_be32s(f, &env->CP0_BadInstrP);
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}
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qemu_get_sbe32s(f, &env->CP0_Count);
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qemu_get_betls(f, &env->CP0_EntryHi);
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qemu_get_sbe32s(f, &env->CP0_Compare);
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@ -319,8 +323,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
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qemu_get_betls(f, &env->CP0_ErrorEPC);
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qemu_get_sbe32s(f, &env->CP0_DESAVE);
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if (version_id >= 5) {
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qemu_get_be32s(f, &env->CP0_BadInstr);
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qemu_get_be32s(f, &env->CP0_BadInstrP);
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for (i = 0; i < MIPS_KSCRATCH_NUM; i++) {
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qemu_get_betls(f, &env->CP0_KScratch[i]);
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}
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