mirrors/qemu
0
0
Fork 0
mirror of https://github.com/qemu/qemu.git synced 2024-11-24 03:13:44 +08:00
Code Issues Packages Projects Releases Wiki Activity

target-sh4: implement negc using TCG

Browse Source 
Using setcond it's now possible to generate a relatively short negc
instruction in TCG.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno 2011-01-13 08:20:39 +01:00
parent 2411fde9a4
commit b2d9eda5d4
3 changed files with 15 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
target-sh4/helper.h
View File

@ -17,7 +17,6 @@ DEF_HELPER_2(addv, i32, i32, i32)
DEF_HELPER_2(addc, i32, i32, i32)
DEF_HELPER_2(subv, i32, i32, i32)
DEF_HELPER_2(subc, i32, i32, i32)
DEF_HELPER_1(negc, i32, i32)
DEF_HELPER_2(div1, i32, i32, i32)
DEF_HELPER_2(macl, void, i32, i32)
DEF_HELPER_2(macw, void, i32, i32)

15
target-sh4/op_helper.c
View File

@ -379,21 +379,6 @@ void helper_macw(uint32_t arg0, uint32_t arg1)
}
}
uint32_t helper_negc(uint32_t arg)
{
uint32_t temp;
temp = -arg;
arg = temp - (env->sr & SR_T);
if (0 < temp)
env->sr |= SR_T;
else
env->sr &= ~SR_T;
if (temp < arg)
env->sr |= SR_T;
return arg;
}
uint32_t helper_subc(uint32_t arg0, uint32_t arg1)
{
uint32_t tmp0, tmp1;

16
target-sh4/translate.c
View File

@ -952,7 +952,21 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_neg_i32(REG(B11_8), REG(B7_4));
return;
case 0x600a: /* negc Rm,Rn */
gen_helper_negc(REG(B11_8), REG(B7_4));
{
TCGv t0, t1;
t0 = tcg_temp_new();
tcg_gen_neg_i32(t0, REG(B7_4));
t1 = tcg_temp_new();
tcg_gen_andi_i32(t1, cpu_sr, SR_T);
tcg_gen_sub_i32(REG(B11_8), t0, t1);
tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
tcg_gen_setcond_i32(TCG_COND_GE, t1, REG(B11_8), t0);
tcg_gen_or_i32(cpu_sr, cpu_sr, t1);
tcg_gen_setcondi_i32(TCG_COND_GE, t1, t0, 0);
tcg_gen_or_i32(cpu_sr, cpu_sr, t1);
tcg_temp_free(t0);
tcg_temp_free(t1);
}
return;
case 0x6007: /* not Rm,Rn */
tcg_gen_not_i32(REG(B11_8), REG(B7_4));