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hw/intc: GICv3 ITS Feature enablement
Added properties to enable ITS feature and define qemu system address space memory in gicv3 common,setup distributor and redistributor registers to indicate LPI support. Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Message-id: 20210910143951.92242-6-shashi.mallela@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -345,6 +345,11 @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
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return;
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return;
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}
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}
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if (s->lpi_enable && !s->dma) {
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error_setg(errp, "Redist-ITS: Guest 'sysmem' reference link not set");
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return;
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}
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s->cpu = g_new0(GICv3CPUState, s->num_cpu);
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s->cpu = g_new0(GICv3CPUState, s->num_cpu);
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for (i = 0; i < s->num_cpu; i++) {
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for (i = 0; i < s->num_cpu; i++) {
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@ -381,6 +386,10 @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
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(1 << 24) |
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(1 << 24) |
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(i << 8) |
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(i << 8) |
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(last << 4);
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(last << 4);
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if (s->lpi_enable) {
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s->cpu[i].gicr_typer |= GICR_TYPER_PLPIS;
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}
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}
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}
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}
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}
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@ -494,9 +503,12 @@ static Property arm_gicv3_common_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1),
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DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1),
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DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
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DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
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DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
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DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
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DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0),
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DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
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DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
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DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions,
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DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions,
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redist_region_count, qdev_prop_uint32, uint32_t),
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redist_region_count, qdev_prop_uint32, uint32_t),
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DEFINE_PROP_LINK("sysmem", GICv3State, dma, TYPE_MEMORY_REGION,
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MemoryRegion *),
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DEFINE_PROP_END_OF_LIST(),
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DEFINE_PROP_END_OF_LIST(),
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};
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};
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@ -384,7 +384,9 @@ static bool gicd_readl(GICv3State *s, hwaddr offset,
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* A3V == 1 (non-zero values of Affinity level 3 supported)
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* A3V == 1 (non-zero values of Affinity level 3 supported)
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* IDbits == 0xf (we support 16-bit interrupt identifiers)
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* IDbits == 0xf (we support 16-bit interrupt identifiers)
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* DVIS == 0 (Direct virtual LPI injection not supported)
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* DVIS == 0 (Direct virtual LPI injection not supported)
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* LPIS == 0 (LPIs not supported)
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* LPIS == 1 (LPIs are supported if affinity routing is enabled)
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* num_LPIs == 0b00000 (bits [15:11],Number of LPIs as indicated
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* by GICD_TYPER.IDbits)
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* MBIS == 0 (message-based SPIs not supported)
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* MBIS == 0 (message-based SPIs not supported)
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* SecurityExtn == 1 if security extns supported
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* SecurityExtn == 1 if security extns supported
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* CPUNumber == 0 since for us ARE is always 1
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* CPUNumber == 0 since for us ARE is always 1
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@ -399,6 +401,7 @@ static bool gicd_readl(GICv3State *s, hwaddr offset,
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bool sec_extn = !(s->gicd_ctlr & GICD_CTLR_DS);
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bool sec_extn = !(s->gicd_ctlr & GICD_CTLR_DS);
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*data = (1 << 25) | (1 << 24) | (sec_extn << 10) |
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*data = (1 << 25) | (1 << 24) | (sec_extn << 10) |
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(s->lpi_enable << GICD_TYPER_LPIS_SHIFT) |
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(0xf << 19) | itlinesnumber;
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(0xf << 19) | itlinesnumber;
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return true;
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return true;
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}
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}
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@ -248,10 +248,16 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset,
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case GICR_CTLR:
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case GICR_CTLR:
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/* For our implementation, GICR_TYPER.DPGS is 0 and so all
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/* For our implementation, GICR_TYPER.DPGS is 0 and so all
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* the DPG bits are RAZ/WI. We don't do anything asynchronously,
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* the DPG bits are RAZ/WI. We don't do anything asynchronously,
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* so UWP and RWP are RAZ/WI. And GICR_TYPER.LPIS is 0 (we don't
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* so UWP and RWP are RAZ/WI. GICR_TYPER.LPIS is 1 (we
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* implement LPIs) so Enable_LPIs is RES0. So there are no writable
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* implement LPIs) so Enable_LPIs is programmable.
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* bits for us.
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*/
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*/
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if (cs->gicr_typer & GICR_TYPER_PLPIS) {
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if (value & GICR_CTLR_ENABLE_LPIS) {
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cs->gicr_ctlr |= GICR_CTLR_ENABLE_LPIS;
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} else {
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cs->gicr_ctlr &= ~GICR_CTLR_ENABLE_LPIS;
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}
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}
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return MEMTX_OK;
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return MEMTX_OK;
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case GICR_STATUSR:
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case GICR_STATUSR:
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/* RAZ/WI for our implementation */
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/* RAZ/WI for our implementation */
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@ -68,6 +68,8 @@
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#define GICD_CTLR_E1NWF (1U << 7)
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#define GICD_CTLR_E1NWF (1U << 7)
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#define GICD_CTLR_RWP (1U << 31)
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#define GICD_CTLR_RWP (1U << 31)
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#define GICD_TYPER_LPIS_SHIFT 17
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/* 16 bits EventId */
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/* 16 bits EventId */
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#define GICD_TYPER_IDBITS 0xf
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#define GICD_TYPER_IDBITS 0xf
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@ -221,6 +221,7 @@ struct GICv3State {
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uint32_t num_cpu;
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uint32_t num_cpu;
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uint32_t num_irq;
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uint32_t num_irq;
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uint32_t revision;
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uint32_t revision;
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bool lpi_enable;
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bool security_extn;
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bool security_extn;
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bool irq_reset_nonsecure;
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bool irq_reset_nonsecure;
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bool gicd_no_migration_shift_bug;
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bool gicd_no_migration_shift_bug;
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