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target/sparc: Move BPr to decodetree

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Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-10-01 16:23:14 -07:00
parent 276567aaf6
commit ab9ffe988a
2 changed files with 25 additions and 41 deletions
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3
target/sparc/insns.decode
View File

@ -7,4 +7,7 @@
BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc
Bicc 00 a:1 cond:4 010 i:s22 &bcc cc=0
%d16 20:s2 0:14
BPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=%d16
CALL 01 i:s30

63
target/sparc/translate.c
View File

@ -1336,14 +1336,13 @@ static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
}
}
#ifdef TARGET_SPARC64
// Inverted logic
static const int gen_tcg_cond_reg[8] = {
-1,
static const TCGCond gen_tcg_cond_reg[8] = {
TCG_COND_NEVER, /* reserved */
TCG_COND_NE,
TCG_COND_GT,
TCG_COND_GE,
-1,
TCG_COND_NEVER, /* reserved */
TCG_COND_EQ,
TCG_COND_LE,
TCG_COND_LT,
@ -1357,16 +1356,6 @@ static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src)
cmp->c2 = tcg_constant_tl(0);
}
static void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
{
DisasCompare cmp;
gen_compare_reg(&cmp, cond, r_src);
/* The interface is to return a boolean in r_dst. */
tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
}
#endif
static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
{
unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
@ -1406,24 +1395,6 @@ static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
}
#ifdef TARGET_SPARC64
static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
TCGv r_reg)
{
unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
target_ulong target = dc->pc + offset;
if (unlikely(AM_CHECK(dc))) {
target &= 0xffffffffULL;
}
flush_cond(dc);
gen_cond_reg(cpu_cond, cond, r_reg);
if (a) {
gen_branch_a(dc, target);
} else {
gen_branch_n(dc, target);
}
}
static void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
{
switch (fccno) {
@ -3063,6 +3034,24 @@ static bool do_bpcc(DisasContext *dc, arg_bcc *a)
TRANS(Bicc, ALL, do_bpcc, a)
TRANS(BPcc, 64, do_bpcc, a)
static bool trans_BPr(DisasContext *dc, arg_BPr *a)
{
target_long target = address_mask_i(dc, dc->pc + a->i * 4);
DisasCompare cmp;
if (!avail_64(dc)) {
return false;
}
if (gen_tcg_cond_reg[a->cond] == TCG_COND_NEVER) {
return false;
}
flush_cond(dc);
gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1));
tcg_gen_setcond_tl(cmp.cond, cpu_cond, cmp.c1, cmp.c2);
return advance_jump_cond(dc, a->a, target);
}
static bool trans_CALL(DisasContext *dc, arg_CALL *a)
{
target_long target = address_mask_i(dc, dc->pc + a->i * 4);
@ -3102,15 +3091,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
case 0x1: /* V9 BPcc */
g_assert_not_reached(); /* in decodetree */
case 0x3: /* V9 BPr */
{
target = GET_FIELD_SP(insn, 0, 13) |
(GET_FIELD_SP(insn, 20, 21) << 14);
target = sign_extend(target, 16);
target <<= 2;
cpu_src1 = get_src1(dc, insn);
do_branch_reg(dc, target, insn, cpu_src1);
goto jmp_insn;
}
g_assert_not_reached(); /* in decodetree */
case 0x5: /* V9 FBPcc */
{
int cc = GET_FIELD_SP(insn, 20, 21);