mirrors/qemu
0
0
Fork 0
mirror of https://github.com/qemu/qemu.git synced 2024-11-25 20:03:37 +08:00
Code Issues Packages Projects Releases Wiki Activity

tcg/ppc: Implement eqv, nand and nor

Browse Source 
Signed-off-by: malc <av1474@comtv.ru>
This commit is contained in:
malc 2010-04-05 16:08:47 +04:00
parent 355b194369
commit aa77bebd98
2 changed files with 17 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
tcg/ppc/tcg-target.c
View File

@ -369,6 +369,8 @@ static int tcg_target_const_match(tcg_target_long val,
#define NOR XO31(124)
#define ANDC XO31( 60)
#define ORC XO31(412)
#define EQV XO31(284)
#define NAND XO31(476)
#define LBZX XO31( 87)
#define LHZX XO31(279)
@ -1475,6 +1477,15 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
case INDEX_op_orc_i32:
tcg_out32 (s, ORC | SAB (args[1], args[0], args[2]));
break;
case INDEX_op_eqv_i32:
tcg_out32 (s, EQV | SAB (args[1], args[0], args[2]));
break;
case INDEX_op_nand_i32:
tcg_out32 (s, NAND | SAB (args[1], args[0], args[2]));
break;
case INDEX_op_nor_i32:
tcg_out32 (s, NOR | SAB (args[1], args[0], args[2]));
break;
case INDEX_op_mul_i32:
if (const_args[2]) {
@ -1758,6 +1769,9 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_andc_i32, { "r", "r", "r" } },
{ INDEX_op_orc_i32, { "r", "r", "r" } },
{ INDEX_op_eqv_i32, { "r", "r", "r" } },
{ INDEX_op_nand_i32, { "r", "r", "r" } },
{ INDEX_op_nor_i32, { "r", "r", "r" } },
{ INDEX_op_setcond_i32, { "r", "r", "ri" } },
{ INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },

6
tcg/ppc/tcg-target.h
View File

@ -89,9 +89,9 @@ enum {
#define TCG_TARGET_HAS_neg_i32
#define TCG_TARGET_HAS_andc_i32
#define TCG_TARGET_HAS_orc_i32
/* #define TCG_TARGET_HAS_eqv_i32 */
/* #define TCG_TARGET_HAS_nand_i32 */
/* #define TCG_TARGET_HAS_nor_i32 */
#define TCG_TARGET_HAS_eqv_i32
#define TCG_TARGET_HAS_nand_i32
#define TCG_TARGET_HAS_nor_i32
#define TCG_AREG0 TCG_REG_R27