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hw/block/pflash_cfi02: Implement multi-sector erase
After two unlock cycles and a sector erase command, the AMD flash chips start a 50 us erase time out. Any additional sector erase commands add a sector to be erased and restart the 50 us timeout. During the timeout, status bit DQ3 is cleared. After the time out, DQ3 is asserted during erasure. Signed-off-by: Stephen Checkoway <stephen.checkoway@oberlin.edu> Message-Id: <20190426162624.55977-9-stephen.checkoway@oberlin.edu> Acked-by: Thomas Huth <thuth@redhat.com> Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com> [PMD: Rebased] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
This commit is contained in:
Stephen Checkoway
Philippe Mathieu-Daudé
parent
a979104239
commit
a50547aca5
@ -31,7 +31,6 @@
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* It does not support flash interleaving.
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* It does not implement software data protection as found in many real chips
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* It does not implement erase suspend/resume commands
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* It does not implement multiple sectors erase
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*/
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#include "qemu/osdep.h"
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@ -106,6 +105,7 @@ struct PFlashCFI02 {
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MemoryRegion orig_mem;
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int rom_mode;
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int read_counter; /* used for lazy switch-back to rom mode */
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int sectors_to_erase;
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char *name;
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void *storage;
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};
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@ -135,6 +135,22 @@ static inline void toggle_dq6(PFlashCFI02 *pfl)
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pfl->status ^= 0x40;
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}
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/*
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* Turn on DQ3.
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*/
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static inline void assert_dq3(PFlashCFI02 *pfl)
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{
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pfl->status |= 0x08;
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}
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/*
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* Turn off DQ3.
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*/
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static inline void reset_dq3(PFlashCFI02 *pfl)
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{
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pfl->status &= ~0x08;
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}
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/*
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* Set up replicated mappings of the same region.
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*/
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@ -163,11 +179,37 @@ static size_t pflash_regions_count(PFlashCFI02 *pfl)
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return pfl->cfi_table[0x2c];
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}
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static void pflash_timer (void *opaque)
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static void pflash_timer(void *opaque)
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{
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PFlashCFI02 *pfl = opaque;
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trace_pflash_timer_expired(pfl->cmd);
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if (pfl->cmd == 0x30) {
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/*
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* Sector erase. If DQ3 is 0 when the timer expires, then the 50
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* us erase timeout has expired so we need to start the timer for the
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* sector erase algorithm. Otherwise, the erase completed and we should
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* go back to read array mode.
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*/
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if ((pfl->status & 0x08) == 0) {
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assert_dq3(pfl);
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/*
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* CFI address 0x21 is "Typical timeout per individual block erase
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* 2^N ms"
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*/
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uint64_t timeout = ((1ULL << pfl->cfi_table[0x21]) *
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pfl->sectors_to_erase) * 1000000;
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timer_mod(&pfl->timer,
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qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout);
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DPRINTF("%s: erase timeout fired; erasing %d sectors\n",
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__func__, pfl->sectors_to_erase);
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return;
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}
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DPRINTF("%s: sector erase complete\n", __func__);
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pfl->sectors_to_erase = 0;
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reset_dq3(pfl);
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}
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/* Reset flash */
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toggle_dq7(pfl);
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if (pfl->bypass) {
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@ -299,6 +341,24 @@ static void pflash_update(PFlashCFI02 *pfl, int offset, int size)
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}
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}
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static void pflash_sector_erase(PFlashCFI02 *pfl, hwaddr offset)
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{
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uint64_t sector_len = pflash_sector_len(pfl, offset);
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offset &= ~(sector_len - 1);
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DPRINTF("%s: start sector erase at %0*" PRIx64 "-%0*" PRIx64 "\n",
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__func__, pfl->width * 2, offset,
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pfl->width * 2, offset + sector_len - 1);
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if (!pfl->ro) {
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uint8_t *p = pfl->storage;
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memset(p + offset, 0xff, sector_len);
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pflash_update(pfl, offset, sector_len);
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}
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set_dq7(pfl, 0x00);
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++pfl->sectors_to_erase;
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/* Set (or reset) the 50 us timer for additional erase commands. */
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timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 50000);
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}
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static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned int width)
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{
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@ -306,7 +366,6 @@ static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
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hwaddr boff;
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uint8_t *p;
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uint8_t cmd;
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uint32_t sector_len;
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trace_pflash_io_write(offset, width, width << 1, value, pfl->wcycle);
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cmd = value;
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@ -469,20 +528,7 @@ static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
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break;
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case 0x30:
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/* Sector erase */
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p = pfl->storage;
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sector_len = pflash_sector_len(pfl, offset);
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offset &= ~(sector_len - 1);
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DPRINTF("%s: start sector erase at %0*" PRIx64 "-%0*" PRIx64 "\n",
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__func__, pfl->width * 2, offset,
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pfl->width * 2, offset + sector_len - 1);
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if (!pfl->ro) {
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memset(p + offset, 0xff, sector_len);
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pflash_update(pfl, offset, sector_len);
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}
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set_dq7(pfl, 0x00);
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/* Let's wait 1/2 second before sector erase is done */
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timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
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(NANOSECONDS_PER_SECOND / 2));
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pflash_sector_erase(pfl, offset);
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break;
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default:
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DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
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@ -496,7 +542,19 @@ static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
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/* Ignore writes during chip erase */
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return;
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case 0x30:
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/* Ignore writes during sector erase */
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/*
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* If DQ3 is 0, additional sector erase commands can be
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* written and anything else (other than an erase suspend) resets
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* the device.
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*/
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if ((pfl->status & 0x08) == 0) {
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if (cmd == 0x30) {
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pflash_sector_erase(pfl, offset);
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} else {
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goto reset_flash;
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}
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}
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/* Ignore writes during the actual erase. */
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return;
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default:
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/* Should never happen */
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@ -35,6 +35,7 @@ typedef struct {
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#define CFI_CMD 0x98
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#define UNLOCK0_CMD 0xAA
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#define UNLOCK1_CMD 0x55
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#define SECOND_UNLOCK_CMD 0x80
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#define AUTOSELECT_CMD 0x90
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#define RESET_CMD 0xF0
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#define PROGRAM_CMD 0xA0
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@ -196,7 +197,7 @@ static void reset(const FlashConfig *c)
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static void sector_erase(const FlashConfig *c, uint64_t byte_addr)
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{
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unlock(c);
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flash_cmd(c, UNLOCK0_ADDR, 0x80);
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flash_cmd(c, UNLOCK0_ADDR, SECOND_UNLOCK_CMD);
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unlock(c);
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flash_write(c, byte_addr, replicate(c, SECTOR_ERASE_CMD));
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}
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@ -235,7 +236,7 @@ static void program(const FlashConfig *c, uint64_t byte_addr, uint16_t data)
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static void chip_erase(const FlashConfig *c)
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{
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unlock(c);
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flash_cmd(c, UNLOCK0_ADDR, 0x80);
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flash_cmd(c, UNLOCK0_ADDR, SECOND_UNLOCK_CMD);
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unlock(c);
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flash_cmd(c, UNLOCK0_ADDR, CHIP_ERASE_CMD);
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}
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@ -315,6 +316,8 @@ static void test_geometry(const void *opaque)
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const uint64_t dq7 = replicate(c, 0x80);
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const uint64_t dq6 = replicate(c, 0x40);
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const uint64_t dq3 = replicate(c, 0x08);
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uint64_t byte_addr = 0;
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for (int region = 0; region < nb_erase_regions; ++region) {
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uint64_t base = 0x2D + 4 * region;
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@ -330,18 +333,29 @@ static void test_geometry(const void *opaque)
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/* Erase and program sector. */
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for (uint32_t i = 0; i < nb_sectors; ++i) {
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sector_erase(c, byte_addr);
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/* Read toggle. */
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/* Check that DQ3 is 0. */
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g_assert_cmphex(flash_read(c, byte_addr) & dq3, ==, 0);
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qtest_clock_step_next(c->qtest); /* Step over the 50 us timeout. */
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/* Check that DQ3 is 1. */
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uint64_t status0 = flash_read(c, byte_addr);
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g_assert_cmphex(status0 & dq3, ==, dq3);
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/* DQ7 is 0 during an erase. */
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g_assert_cmphex(status0 & dq7, ==, 0);
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uint64_t status1 = flash_read(c, byte_addr);
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/* DQ6 toggles during an erase. */
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g_assert_cmphex(status0 & dq6, ==, ~status1 & dq6);
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/* Wait for erase to complete. */
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qtest_clock_step_next(c->qtest);
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wait_for_completion(c, byte_addr);
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/* Ensure DQ6 has stopped toggling. */
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g_assert_cmphex(flash_read(c, byte_addr), ==,
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flash_read(c, byte_addr));
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/* Now the data should be valid. */
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g_assert_cmphex(flash_read(c, byte_addr), ==, bank_mask(c));
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@ -404,6 +418,44 @@ static void test_geometry(const void *opaque)
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g_assert_cmphex(flash_query(c, FLASH_ADDR(0)), ==, replicate(c, 0xBF));
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reset(c);
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/*
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* Program a word on each sector, erase one or two sectors per region, and
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* verify that all of those, and only those, are erased.
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*/
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byte_addr = 0;
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for (int region = 0; region < nb_erase_regions; ++region) {
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for (int i = 0; i < config->nb_blocs[region]; ++i) {
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program(c, byte_addr, 0);
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byte_addr += config->sector_len[region];
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}
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}
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unlock(c);
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flash_cmd(c, UNLOCK0_ADDR, SECOND_UNLOCK_CMD);
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unlock(c);
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byte_addr = 0;
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const uint64_t erase_cmd = replicate(c, SECTOR_ERASE_CMD);
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for (int region = 0; region < nb_erase_regions; ++region) {
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flash_write(c, byte_addr, erase_cmd);
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if (c->nb_blocs[region] > 1) {
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flash_write(c, byte_addr + c->sector_len[region], erase_cmd);
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}
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byte_addr += c->sector_len[region] * c->nb_blocs[region];
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}
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qtest_clock_step_next(c->qtest); /* Step over the 50 us timeout. */
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wait_for_completion(c, 0);
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byte_addr = 0;
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for (int region = 0; region < nb_erase_regions; ++region) {
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for (int i = 0; i < config->nb_blocs[region]; ++i) {
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if (i < 2) {
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g_assert_cmphex(flash_read(c, byte_addr), ==, bank_mask(c));
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} else {
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g_assert_cmphex(flash_read(c, byte_addr), ==, 0);
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}
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byte_addr += config->sector_len[region];
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}
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}
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qtest_quit(qtest);
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}
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@ -428,17 +480,17 @@ static void test_cfi_in_autoselect(const void *opaque)
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/* 1. Enter autoselect. */
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unlock(c);
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flash_cmd(c, UNLOCK0_ADDR, AUTOSELECT_CMD);
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g_assert_cmpint(flash_query(c, FLASH_ADDR(0)), ==, replicate(c, 0xBF));
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g_assert_cmphex(flash_query(c, FLASH_ADDR(0)), ==, replicate(c, 0xBF));
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/* 2. Enter CFI. */
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flash_cmd(c, CFI_ADDR, CFI_CMD);
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g_assert_cmpint(flash_query(c, FLASH_ADDR(0x10)), ==, replicate(c, 'Q'));
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g_assert_cmpint(flash_query(c, FLASH_ADDR(0x11)), ==, replicate(c, 'R'));
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g_assert_cmpint(flash_query(c, FLASH_ADDR(0x12)), ==, replicate(c, 'Y'));
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g_assert_cmphex(flash_query(c, FLASH_ADDR(0x10)), ==, replicate(c, 'Q'));
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g_assert_cmphex(flash_query(c, FLASH_ADDR(0x11)), ==, replicate(c, 'R'));
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g_assert_cmphex(flash_query(c, FLASH_ADDR(0x12)), ==, replicate(c, 'Y'));
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/* 3. Exit CFI. */
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reset(c);
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g_assert_cmpint(flash_query(c, FLASH_ADDR(0)), ==, replicate(c, 0xBF));
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g_assert_cmphex(flash_query(c, FLASH_ADDR(0)), ==, replicate(c, 0xBF));
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qtest_quit(qtest);
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}
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