mirrors/qemu
0
0
Fork 0
mirror of https://github.com/qemu/qemu.git synced 2024-11-26 04:13:39 +08:00
Code Issues Packages Projects Releases Wiki Activity

target-ppc: Fix openpic timer read register offset

Browse Source 
openpic_tmr_read() is incorrectly computing register offset of the
TCCR, TBCR, TVPR, and TDR registers when accessing the open pic timer
registers.  Specifically the offset of timer registers for
openpic_tmr_read() is not accounting for the timer frequency reporting
register (TFFR) which is the first register in the "tmr" memory
region.

openpic_tmr_write() *is* correctly computing the offset by adding
0x10f0 to the address prior to computing the register index.  This
patch instead subtracts 0x10 in both the read and write routines and
eliminates some other gratuitous differences between the functions.

Signed-off-by: Aaron Larson <alarson@ddci.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Aaron Larson 2017-06-02 04:32:59 -07:00 committed by David Gibson
parent 0b55aa91c9
commit a09f7443bc
1 changed files with 10 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
hw/intc/openpic.c
View File

@ -796,27 +796,24 @@ static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len)
} }
static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val, static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val,
unsigned len) unsigned len)
{ {
OpenPICState *opp = opaque; OpenPICState *opp = opaque;
int idx; int idx;
addr += 0x10f0;
DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n", DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n",
__func__, addr, val); __func__, (addr + 0x10f0), val);
if (addr & 0xF) { if (addr & 0xF) {
return; return;
} }
if (addr == 0x10f0) { if (addr == 0) {
/* TFRR */ /* TFRR */
opp->tfrr = val; opp->tfrr = val;
return; return;
} }
addr -= 0x10; /* correct for TFRR */
idx = (addr >> 6) & 0x3; idx = (addr >> 6) & 0x3;
addr = addr & 0x30;
switch (addr & 0x30) { switch (addr & 0x30) {
case 0x00: /* TCCR */ case 0x00: /* TCCR */
@ -844,16 +841,17 @@ static uint64_t openpic_tmr_read(void *opaque, hwaddr addr, unsigned len)
uint32_t retval = -1; uint32_t retval = -1;
int idx; int idx;
DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr + 0x10f0);
if (addr & 0xF) { if (addr & 0xF) {
goto out; goto out;
} }
idx = (addr >> 6) & 0x3; if (addr == 0) {
if (addr == 0x0) {
/* TFRR */ /* TFRR */
retval = opp->tfrr; retval = opp->tfrr;
goto out; goto out;
} }
addr -= 0x10; /* correct for TFRR */
idx = (addr >> 6) & 0x3;
switch (addr & 0x30) { switch (addr & 0x30) {
case 0x00: /* TCCR */ case 0x00: /* TCCR */
retval = opp->timers[idx].tccr; retval = opp->timers[idx].tccr;
@ -861,10 +859,10 @@ static uint64_t openpic_tmr_read(void *opaque, hwaddr addr, unsigned len)
case 0x10: /* TBCR */ case 0x10: /* TBCR */
retval = opp->timers[idx].tbcr; retval = opp->timers[idx].tbcr;
break; break;
case 0x20: /* TIPV */ case 0x20: /* TVPR */
retval = read_IRQreg_ivpr(opp, opp->irq_tim0 + idx); retval = read_IRQreg_ivpr(opp, opp->irq_tim0 + idx);
break; break;
case 0x30: /* TIDE (TIDR) */ case 0x30: /* TDR */
retval = read_IRQreg_idr(opp, opp->irq_tim0 + idx); retval = read_IRQreg_idr(opp, opp->irq_tim0 + idx);
break; break;
} }