mirror of
https://github.com/qemu/qemu.git
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Merge branch 'target-arm.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm
This commit is contained in:
Andrzej Zaborowski
commit
9f60639b84
@ -419,6 +419,82 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
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}
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#endif
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/*----------------------------------------------------------------------------
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| Select which NaN to propagate for a three-input operation.
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| For the moment we assume that no CPU needs the 'larger significand'
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| information.
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| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
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*----------------------------------------------------------------------------*/
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#if defined(TARGET_ARM)
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static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
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flag cIsQNaN, flag cIsSNaN, flag infzero STATUS_PARAM)
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{
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/* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
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* the default NaN
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*/
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if (infzero && cIsQNaN) {
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float_raise(float_flag_invalid STATUS_VAR);
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return 3;
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}
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/* This looks different from the ARM ARM pseudocode, because the ARM ARM
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* puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
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*/
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if (cIsSNaN) {
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return 2;
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} else if (aIsSNaN) {
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return 0;
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} else if (bIsSNaN) {
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return 1;
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} else if (cIsQNaN) {
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return 2;
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} else if (aIsQNaN) {
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return 0;
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} else {
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return 1;
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}
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}
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#elif defined(TARGET_PPC)
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static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
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flag cIsQNaN, flag cIsSNaN, flag infzero STATUS_PARAM)
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{
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/* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
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* to return an input NaN if we have one (ie c) rather than generating
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* a default NaN
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*/
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if (infzero) {
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float_raise(float_flag_invalid STATUS_VAR);
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return 2;
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}
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/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
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* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
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*/
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if (aIsSNaN || aIsQNaN) {
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return 0;
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} else if (cIsSNaN || cIsQNaN) {
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return 2;
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} else {
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return 1;
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}
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}
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#else
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/* A default implementation: prefer a to b to c.
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* This is unlikely to actually match any real implementation.
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*/
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static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
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flag cIsQNaN, flag cIsSNaN, flag infzero STATUS_PARAM)
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{
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if (aIsSNaN || aIsQNaN) {
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return 0;
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} else if (bIsSNaN || bIsQNaN) {
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return 1;
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} else {
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return 2;
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}
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}
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#endif
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/*----------------------------------------------------------------------------
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| Takes two single-precision floating-point values `a' and `b', one of which
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| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
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@ -459,6 +535,57 @@ static float32 propagateFloat32NaN( float32 a, float32 b STATUS_PARAM)
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}
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}
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/*----------------------------------------------------------------------------
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| Takes three single-precision floating-point values `a', `b' and `c', one of
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| which is a NaN, and returns the appropriate NaN result. If any of `a',
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| `b' or `c' is a signaling NaN, the invalid exception is raised.
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| The input infzero indicates whether a*b was 0*inf or inf*0 (in which case
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| obviously c is a NaN, and whether to propagate c or some other NaN is
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| implementation defined).
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*----------------------------------------------------------------------------*/
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static float32 propagateFloat32MulAddNaN(float32 a, float32 b,
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float32 c, flag infzero STATUS_PARAM)
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{
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flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
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cIsQuietNaN, cIsSignalingNaN;
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int which;
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aIsQuietNaN = float32_is_quiet_nan(a);
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aIsSignalingNaN = float32_is_signaling_nan(a);
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bIsQuietNaN = float32_is_quiet_nan(b);
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bIsSignalingNaN = float32_is_signaling_nan(b);
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cIsQuietNaN = float32_is_quiet_nan(c);
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cIsSignalingNaN = float32_is_signaling_nan(c);
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if (aIsSignalingNaN | bIsSignalingNaN | cIsSignalingNaN) {
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float_raise(float_flag_invalid STATUS_VAR);
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}
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which = pickNaNMulAdd(aIsQuietNaN, aIsSignalingNaN,
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bIsQuietNaN, bIsSignalingNaN,
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cIsQuietNaN, cIsSignalingNaN, infzero STATUS_VAR);
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if (STATUS(default_nan_mode)) {
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/* Note that this check is after pickNaNMulAdd so that function
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* has an opportunity to set the Invalid flag.
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*/
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return float32_default_nan;
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}
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switch (which) {
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case 0:
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return float32_maybe_silence_nan(a);
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case 1:
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return float32_maybe_silence_nan(b);
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case 2:
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return float32_maybe_silence_nan(c);
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case 3:
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default:
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return float32_default_nan;
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}
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}
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/*----------------------------------------------------------------------------
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| Returns 1 if the double-precision floating-point value `a' is a quiet
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| NaN; otherwise returns 0.
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@ -595,6 +722,57 @@ static float64 propagateFloat64NaN( float64 a, float64 b STATUS_PARAM)
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}
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}
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/*----------------------------------------------------------------------------
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| Takes three double-precision floating-point values `a', `b' and `c', one of
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| which is a NaN, and returns the appropriate NaN result. If any of `a',
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| `b' or `c' is a signaling NaN, the invalid exception is raised.
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| The input infzero indicates whether a*b was 0*inf or inf*0 (in which case
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| obviously c is a NaN, and whether to propagate c or some other NaN is
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| implementation defined).
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*----------------------------------------------------------------------------*/
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static float64 propagateFloat64MulAddNaN(float64 a, float64 b,
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float64 c, flag infzero STATUS_PARAM)
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{
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flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
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cIsQuietNaN, cIsSignalingNaN;
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int which;
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aIsQuietNaN = float64_is_quiet_nan(a);
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aIsSignalingNaN = float64_is_signaling_nan(a);
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bIsQuietNaN = float64_is_quiet_nan(b);
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bIsSignalingNaN = float64_is_signaling_nan(b);
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cIsQuietNaN = float64_is_quiet_nan(c);
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cIsSignalingNaN = float64_is_signaling_nan(c);
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if (aIsSignalingNaN | bIsSignalingNaN | cIsSignalingNaN) {
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float_raise(float_flag_invalid STATUS_VAR);
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}
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which = pickNaNMulAdd(aIsQuietNaN, aIsSignalingNaN,
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bIsQuietNaN, bIsSignalingNaN,
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cIsQuietNaN, cIsSignalingNaN, infzero STATUS_VAR);
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if (STATUS(default_nan_mode)) {
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/* Note that this check is after pickNaNMulAdd so that function
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* has an opportunity to set the Invalid flag.
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*/
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return float64_default_nan;
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}
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switch (which) {
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case 0:
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return float64_maybe_silence_nan(a);
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case 1:
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return float64_maybe_silence_nan(b);
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case 2:
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return float64_maybe_silence_nan(c);
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case 3:
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default:
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return float64_default_nan;
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}
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}
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/*----------------------------------------------------------------------------
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| Returns 1 if the extended double-precision floating-point value `a' is a
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| quiet NaN; otherwise returns 0. This slightly differs from the same
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427
fpu/softfloat.c
427
fpu/softfloat.c
@ -2117,6 +2117,213 @@ float32 float32_rem( float32 a, float32 b STATUS_PARAM )
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}
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/*----------------------------------------------------------------------------
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| Returns the result of multiplying the single-precision floating-point values
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| `a' and `b' then adding 'c', with no intermediate rounding step after the
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| multiplication. The operation is performed according to the IEC/IEEE
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| Standard for Binary Floating-Point Arithmetic 754-2008.
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| The flags argument allows the caller to select negation of the
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| addend, the intermediate product, or the final result. (The difference
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| between this and having the caller do a separate negation is that negating
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| externally will flip the sign bit on NaNs.)
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*----------------------------------------------------------------------------*/
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float32 float32_muladd(float32 a, float32 b, float32 c, int flags STATUS_PARAM)
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{
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flag aSign, bSign, cSign, zSign;
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int aExp, bExp, cExp, pExp, zExp, expDiff;
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uint32_t aSig, bSig, cSig;
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flag pInf, pZero, pSign;
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uint64_t pSig64, cSig64, zSig64;
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uint32_t pSig;
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int shiftcount;
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flag signflip, infzero;
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a = float32_squash_input_denormal(a STATUS_VAR);
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b = float32_squash_input_denormal(b STATUS_VAR);
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c = float32_squash_input_denormal(c STATUS_VAR);
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aSig = extractFloat32Frac(a);
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aExp = extractFloat32Exp(a);
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aSign = extractFloat32Sign(a);
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bSig = extractFloat32Frac(b);
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bExp = extractFloat32Exp(b);
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bSign = extractFloat32Sign(b);
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cSig = extractFloat32Frac(c);
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cExp = extractFloat32Exp(c);
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cSign = extractFloat32Sign(c);
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infzero = ((aExp == 0 && aSig == 0 && bExp == 0xff && bSig == 0) ||
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(aExp == 0xff && aSig == 0 && bExp == 0 && bSig == 0));
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/* It is implementation-defined whether the cases of (0,inf,qnan)
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* and (inf,0,qnan) raise InvalidOperation or not (and what QNaN
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* they return if they do), so we have to hand this information
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* off to the target-specific pick-a-NaN routine.
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*/
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if (((aExp == 0xff) && aSig) ||
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((bExp == 0xff) && bSig) ||
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((cExp == 0xff) && cSig)) {
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return propagateFloat32MulAddNaN(a, b, c, infzero STATUS_VAR);
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}
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if (infzero) {
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float_raise(float_flag_invalid STATUS_VAR);
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return float32_default_nan;
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}
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if (flags & float_muladd_negate_c) {
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cSign ^= 1;
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}
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signflip = (flags & float_muladd_negate_result) ? 1 : 0;
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/* Work out the sign and type of the product */
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pSign = aSign ^ bSign;
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if (flags & float_muladd_negate_product) {
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pSign ^= 1;
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}
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pInf = (aExp == 0xff) || (bExp == 0xff);
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pZero = ((aExp | aSig) == 0) || ((bExp | bSig) == 0);
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if (cExp == 0xff) {
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if (pInf && (pSign ^ cSign)) {
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/* addition of opposite-signed infinities => InvalidOperation */
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float_raise(float_flag_invalid STATUS_VAR);
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return float32_default_nan;
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}
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/* Otherwise generate an infinity of the same sign */
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return packFloat32(cSign ^ signflip, 0xff, 0);
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}
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if (pInf) {
|
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return packFloat32(pSign ^ signflip, 0xff, 0);
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}
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if (pZero) {
|
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if (cExp == 0) {
|
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if (cSig == 0) {
|
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/* Adding two exact zeroes */
|
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if (pSign == cSign) {
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zSign = pSign;
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} else if (STATUS(float_rounding_mode) == float_round_down) {
|
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zSign = 1;
|
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} else {
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zSign = 0;
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}
|
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return packFloat32(zSign ^ signflip, 0, 0);
|
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}
|
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/* Exact zero plus a denorm */
|
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if (STATUS(flush_to_zero)) {
|
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float_raise(float_flag_output_denormal STATUS_VAR);
|
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return packFloat32(cSign ^ signflip, 0, 0);
|
||||
}
|
||||
}
|
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/* Zero plus something non-zero : just return the something */
|
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return c ^ (signflip << 31);
|
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}
|
||||
|
||||
if (aExp == 0) {
|
||||
normalizeFloat32Subnormal(aSig, &aExp, &aSig);
|
||||
}
|
||||
if (bExp == 0) {
|
||||
normalizeFloat32Subnormal(bSig, &bExp, &bSig);
|
||||
}
|
||||
|
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/* Calculate the actual result a * b + c */
|
||||
|
||||
/* Multiply first; this is easy. */
|
||||
/* NB: we subtract 0x7e where float32_mul() subtracts 0x7f
|
||||
* because we want the true exponent, not the "one-less-than"
|
||||
* flavour that roundAndPackFloat32() takes.
|
||||
*/
|
||||
pExp = aExp + bExp - 0x7e;
|
||||
aSig = (aSig | 0x00800000) << 7;
|
||||
bSig = (bSig | 0x00800000) << 8;
|
||||
pSig64 = (uint64_t)aSig * bSig;
|
||||
if ((int64_t)(pSig64 << 1) >= 0) {
|
||||
pSig64 <<= 1;
|
||||
pExp--;
|
||||
}
|
||||
|
||||
zSign = pSign ^ signflip;
|
||||
|
||||
/* Now pSig64 is the significand of the multiply, with the explicit bit in
|
||||
* position 62.
|
||||
*/
|
||||
if (cExp == 0) {
|
||||
if (!cSig) {
|
||||
/* Throw out the special case of c being an exact zero now */
|
||||
shift64RightJamming(pSig64, 32, &pSig64);
|
||||
pSig = pSig64;
|
||||
return roundAndPackFloat32(zSign, pExp - 1,
|
||||
pSig STATUS_VAR);
|
||||
}
|
||||
normalizeFloat32Subnormal(cSig, &cExp, &cSig);
|
||||
}
|
||||
|
||||
cSig64 = (uint64_t)cSig << (62 - 23);
|
||||
cSig64 |= LIT64(0x4000000000000000);
|
||||
expDiff = pExp - cExp;
|
||||
|
||||
if (pSign == cSign) {
|
||||
/* Addition */
|
||||
if (expDiff > 0) {
|
||||
/* scale c to match p */
|
||||
shift64RightJamming(cSig64, expDiff, &cSig64);
|
||||
zExp = pExp;
|
||||
} else if (expDiff < 0) {
|
||||
/* scale p to match c */
|
||||
shift64RightJamming(pSig64, -expDiff, &pSig64);
|
||||
zExp = cExp;
|
||||
} else {
|
||||
/* no scaling needed */
|
||||
zExp = cExp;
|
||||
}
|
||||
/* Add significands and make sure explicit bit ends up in posn 62 */
|
||||
zSig64 = pSig64 + cSig64;
|
||||
if ((int64_t)zSig64 < 0) {
|
||||
shift64RightJamming(zSig64, 1, &zSig64);
|
||||
} else {
|
||||
zExp--;
|
||||
}
|
||||
} else {
|
||||
/* Subtraction */
|
||||
if (expDiff > 0) {
|
||||
shift64RightJamming(cSig64, expDiff, &cSig64);
|
||||
zSig64 = pSig64 - cSig64;
|
||||
zExp = pExp;
|
||||
} else if (expDiff < 0) {
|
||||
shift64RightJamming(pSig64, -expDiff, &pSig64);
|
||||
zSig64 = cSig64 - pSig64;
|
||||
zExp = cExp;
|
||||
zSign ^= 1;
|
||||
} else {
|
||||
zExp = pExp;
|
||||
if (cSig64 < pSig64) {
|
||||
zSig64 = pSig64 - cSig64;
|
||||
} else if (pSig64 < cSig64) {
|
||||
zSig64 = cSig64 - pSig64;
|
||||
zSign ^= 1;
|
||||
} else {
|
||||
/* Exact zero */
|
||||
zSign = signflip;
|
||||
if (STATUS(float_rounding_mode) == float_round_down) {
|
||||
zSign ^= 1;
|
||||
}
|
||||
return packFloat32(zSign, 0, 0);
|
||||
}
|
||||
}
|
||||
--zExp;
|
||||
/* Normalize to put the explicit bit back into bit 62. */
|
||||
shiftcount = countLeadingZeros64(zSig64) - 1;
|
||||
zSig64 <<= shiftcount;
|
||||
zExp -= shiftcount;
|
||||
}
|
||||
shift64RightJamming(zSig64, 32, &zSig64);
|
||||
return roundAndPackFloat32(zSign, zExp, zSig64 STATUS_VAR);
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns the square root of the single-precision floating-point value `a'.
|
||||
| The operation is performed according to the IEC/IEEE Standard for Binary
|
||||
@ -3464,6 +3671,226 @@ float64 float64_rem( float64 a, float64 b STATUS_PARAM )
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns the result of multiplying the double-precision floating-point values
|
||||
| `a' and `b' then adding 'c', with no intermediate rounding step after the
|
||||
| multiplication. The operation is performed according to the IEC/IEEE
|
||||
| Standard for Binary Floating-Point Arithmetic 754-2008.
|
||||
| The flags argument allows the caller to select negation of the
|
||||
| addend, the intermediate product, or the final result. (The difference
|
||||
| between this and having the caller do a separate negation is that negating
|
||||
| externally will flip the sign bit on NaNs.)
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
float64 float64_muladd(float64 a, float64 b, float64 c, int flags STATUS_PARAM)
|
||||
{
|
||||
flag aSign, bSign, cSign, zSign;
|
||||
int aExp, bExp, cExp, pExp, zExp, expDiff;
|
||||
uint64_t aSig, bSig, cSig;
|
||||
flag pInf, pZero, pSign;
|
||||
uint64_t pSig0, pSig1, cSig0, cSig1, zSig0, zSig1;
|
||||
int shiftcount;
|
||||
flag signflip, infzero;
|
||||
|
||||
a = float64_squash_input_denormal(a STATUS_VAR);
|
||||
b = float64_squash_input_denormal(b STATUS_VAR);
|
||||
c = float64_squash_input_denormal(c STATUS_VAR);
|
||||
aSig = extractFloat64Frac(a);
|
||||
aExp = extractFloat64Exp(a);
|
||||
aSign = extractFloat64Sign(a);
|
||||
bSig = extractFloat64Frac(b);
|
||||
bExp = extractFloat64Exp(b);
|
||||
bSign = extractFloat64Sign(b);
|
||||
cSig = extractFloat64Frac(c);
|
||||
cExp = extractFloat64Exp(c);
|
||||
cSign = extractFloat64Sign(c);
|
||||
|
||||
infzero = ((aExp == 0 && aSig == 0 && bExp == 0x7ff && bSig == 0) ||
|
||||
(aExp == 0x7ff && aSig == 0 && bExp == 0 && bSig == 0));
|
||||
|
||||
/* It is implementation-defined whether the cases of (0,inf,qnan)
|
||||
* and (inf,0,qnan) raise InvalidOperation or not (and what QNaN
|
||||
* they return if they do), so we have to hand this information
|
||||
* off to the target-specific pick-a-NaN routine.
|
||||
*/
|
||||
if (((aExp == 0x7ff) && aSig) ||
|
||||
((bExp == 0x7ff) && bSig) ||
|
||||
((cExp == 0x7ff) && cSig)) {
|
||||
return propagateFloat64MulAddNaN(a, b, c, infzero STATUS_VAR);
|
||||
}
|
||||
|
||||
if (infzero) {
|
||||
float_raise(float_flag_invalid STATUS_VAR);
|
||||
return float64_default_nan;
|
||||
}
|
||||
|
||||
if (flags & float_muladd_negate_c) {
|
||||
cSign ^= 1;
|
||||
}
|
||||
|
||||
signflip = (flags & float_muladd_negate_result) ? 1 : 0;
|
||||
|
||||
/* Work out the sign and type of the product */
|
||||
pSign = aSign ^ bSign;
|
||||
if (flags & float_muladd_negate_product) {
|
||||
pSign ^= 1;
|
||||
}
|
||||
pInf = (aExp == 0x7ff) || (bExp == 0x7ff);
|
||||
pZero = ((aExp | aSig) == 0) || ((bExp | bSig) == 0);
|
||||
|
||||
if (cExp == 0x7ff) {
|
||||
if (pInf && (pSign ^ cSign)) {
|
||||
/* addition of opposite-signed infinities => InvalidOperation */
|
||||
float_raise(float_flag_invalid STATUS_VAR);
|
||||
return float64_default_nan;
|
||||
}
|
||||
/* Otherwise generate an infinity of the same sign */
|
||||
return packFloat64(cSign ^ signflip, 0x7ff, 0);
|
||||
}
|
||||
|
||||
if (pInf) {
|
||||
return packFloat64(pSign ^ signflip, 0x7ff, 0);
|
||||
}
|
||||
|
||||
if (pZero) {
|
||||
if (cExp == 0) {
|
||||
if (cSig == 0) {
|
||||
/* Adding two exact zeroes */
|
||||
if (pSign == cSign) {
|
||||
zSign = pSign;
|
||||
} else if (STATUS(float_rounding_mode) == float_round_down) {
|
||||
zSign = 1;
|
||||
} else {
|
||||
zSign = 0;
|
||||
}
|
||||
return packFloat64(zSign ^ signflip, 0, 0);
|
||||
}
|
||||
/* Exact zero plus a denorm */
|
||||
if (STATUS(flush_to_zero)) {
|
||||
float_raise(float_flag_output_denormal STATUS_VAR);
|
||||
return packFloat64(cSign ^ signflip, 0, 0);
|
||||
}
|
||||
}
|
||||
/* Zero plus something non-zero : just return the something */
|
||||
return c ^ ((uint64_t)signflip << 63);
|
||||
}
|
||||
|
||||
if (aExp == 0) {
|
||||
normalizeFloat64Subnormal(aSig, &aExp, &aSig);
|
||||
}
|
||||
if (bExp == 0) {
|
||||
normalizeFloat64Subnormal(bSig, &bExp, &bSig);
|
||||
}
|
||||
|
||||
/* Calculate the actual result a * b + c */
|
||||
|
||||
/* Multiply first; this is easy. */
|
||||
/* NB: we subtract 0x3fe where float64_mul() subtracts 0x3ff
|
||||
* because we want the true exponent, not the "one-less-than"
|
||||
* flavour that roundAndPackFloat64() takes.
|
||||
*/
|
||||
pExp = aExp + bExp - 0x3fe;
|
||||
aSig = (aSig | LIT64(0x0010000000000000))<<10;
|
||||
bSig = (bSig | LIT64(0x0010000000000000))<<11;
|
||||
mul64To128(aSig, bSig, &pSig0, &pSig1);
|
||||
if ((int64_t)(pSig0 << 1) >= 0) {
|
||||
shortShift128Left(pSig0, pSig1, 1, &pSig0, &pSig1);
|
||||
pExp--;
|
||||
}
|
||||
|
||||
zSign = pSign ^ signflip;
|
||||
|
||||
/* Now [pSig0:pSig1] is the significand of the multiply, with the explicit
|
||||
* bit in position 126.
|
||||
*/
|
||||
if (cExp == 0) {
|
||||
if (!cSig) {
|
||||
/* Throw out the special case of c being an exact zero now */
|
||||
shift128RightJamming(pSig0, pSig1, 64, &pSig0, &pSig1);
|
||||
return roundAndPackFloat64(zSign, pExp - 1,
|
||||
pSig1 STATUS_VAR);
|
||||
}
|
||||
normalizeFloat64Subnormal(cSig, &cExp, &cSig);
|
||||
}
|
||||
|
||||
/* Shift cSig and add the explicit bit so [cSig0:cSig1] is the
|
||||
* significand of the addend, with the explicit bit in position 126.
|
||||
*/
|
||||
cSig0 = cSig << (126 - 64 - 52);
|
||||
cSig1 = 0;
|
||||
cSig0 |= LIT64(0x4000000000000000);
|
||||
expDiff = pExp - cExp;
|
||||
|
||||
if (pSign == cSign) {
|
||||
/* Addition */
|
||||
if (expDiff > 0) {
|
||||
/* scale c to match p */
|
||||
shift128RightJamming(cSig0, cSig1, expDiff, &cSig0, &cSig1);
|
||||
zExp = pExp;
|
||||
} else if (expDiff < 0) {
|
||||
/* scale p to match c */
|
||||
shift128RightJamming(pSig0, pSig1, -expDiff, &pSig0, &pSig1);
|
||||
zExp = cExp;
|
||||
} else {
|
||||
/* no scaling needed */
|
||||
zExp = cExp;
|
||||
}
|
||||
/* Add significands and make sure explicit bit ends up in posn 126 */
|
||||
add128(pSig0, pSig1, cSig0, cSig1, &zSig0, &zSig1);
|
||||
if ((int64_t)zSig0 < 0) {
|
||||
shift128RightJamming(zSig0, zSig1, 1, &zSig0, &zSig1);
|
||||
} else {
|
||||
zExp--;
|
||||
}
|
||||
shift128RightJamming(zSig0, zSig1, 64, &zSig0, &zSig1);
|
||||
return roundAndPackFloat64(zSign, zExp, zSig1 STATUS_VAR);
|
||||
} else {
|
||||
/* Subtraction */
|
||||
if (expDiff > 0) {
|
||||
shift128RightJamming(cSig0, cSig1, expDiff, &cSig0, &cSig1);
|
||||
sub128(pSig0, pSig1, cSig0, cSig1, &zSig0, &zSig1);
|
||||
zExp = pExp;
|
||||
} else if (expDiff < 0) {
|
||||
shift128RightJamming(pSig0, pSig1, -expDiff, &pSig0, &pSig1);
|
||||
sub128(cSig0, cSig1, pSig0, pSig1, &zSig0, &zSig1);
|
||||
zExp = cExp;
|
||||
zSign ^= 1;
|
||||
} else {
|
||||
zExp = pExp;
|
||||
if (lt128(cSig0, cSig1, pSig0, pSig1)) {
|
||||
sub128(pSig0, pSig1, cSig0, cSig1, &zSig0, &zSig1);
|
||||
} else if (lt128(pSig0, pSig1, cSig0, cSig1)) {
|
||||
sub128(cSig0, cSig1, pSig0, pSig1, &zSig0, &zSig1);
|
||||
zSign ^= 1;
|
||||
} else {
|
||||
/* Exact zero */
|
||||
zSign = signflip;
|
||||
if (STATUS(float_rounding_mode) == float_round_down) {
|
||||
zSign ^= 1;
|
||||
}
|
||||
return packFloat64(zSign, 0, 0);
|
||||
}
|
||||
}
|
||||
--zExp;
|
||||
/* Do the equivalent of normalizeRoundAndPackFloat64() but
|
||||
* starting with the significand in a pair of uint64_t.
|
||||
*/
|
||||
if (zSig0) {
|
||||
shiftcount = countLeadingZeros64(zSig0) - 1;
|
||||
shortShift128Left(zSig0, zSig1, shiftcount, &zSig0, &zSig1);
|
||||
if (zSig1) {
|
||||
zSig0 |= 1;
|
||||
}
|
||||
zExp -= shiftcount;
|
||||
} else {
|
||||
shiftcount = countLeadingZeros64(zSig1) - 1;
|
||||
zSig0 = zSig1 << shiftcount;
|
||||
zExp -= (shiftcount + 64);
|
||||
}
|
||||
return roundAndPackFloat64(zSign, zExp, zSig0 STATUS_VAR);
|
||||
}
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns the square root of the double-precision floating-point value `a'.
|
||||
| The operation is performed according to the IEC/IEEE Standard for Binary
|
||||
|
||||
@ -211,6 +211,18 @@ void set_floatx80_rounding_precision(int val STATUS_PARAM);
|
||||
*----------------------------------------------------------------------------*/
|
||||
void float_raise( int8 flags STATUS_PARAM);
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Options to indicate which negations to perform in float*_muladd()
|
||||
| Using these differs from negating an input or output before calling
|
||||
| the muladd function in that this means that a NaN doesn't have its
|
||||
| sign bit inverted before it is propagated.
|
||||
*----------------------------------------------------------------------------*/
|
||||
enum {
|
||||
float_muladd_negate_c = 1,
|
||||
float_muladd_negate_product = 2,
|
||||
float_muladd_negate_result = 3,
|
||||
};
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Software IEC/IEEE integer-to-floating-point conversion routines.
|
||||
*----------------------------------------------------------------------------*/
|
||||
@ -269,6 +281,7 @@ float32 float32_sub( float32, float32 STATUS_PARAM );
|
||||
float32 float32_mul( float32, float32 STATUS_PARAM );
|
||||
float32 float32_div( float32, float32 STATUS_PARAM );
|
||||
float32 float32_rem( float32, float32 STATUS_PARAM );
|
||||
float32 float32_muladd(float32, float32, float32, int STATUS_PARAM);
|
||||
float32 float32_sqrt( float32 STATUS_PARAM );
|
||||
float32 float32_exp2( float32 STATUS_PARAM );
|
||||
float32 float32_log2( float32 STATUS_PARAM );
|
||||
@ -375,6 +388,7 @@ float64 float64_sub( float64, float64 STATUS_PARAM );
|
||||
float64 float64_mul( float64, float64 STATUS_PARAM );
|
||||
float64 float64_div( float64, float64 STATUS_PARAM );
|
||||
float64 float64_rem( float64, float64 STATUS_PARAM );
|
||||
float64 float64_muladd(float64, float64, float64, int STATUS_PARAM);
|
||||
float64 float64_sqrt( float64 STATUS_PARAM );
|
||||
float64 float64_log2( float64 STATUS_PARAM );
|
||||
int float64_eq( float64, float64 STATUS_PARAM );
|
||||
|
||||
@ -366,7 +366,7 @@ enum arm_features {
|
||||
ARM_FEATURE_VFP3,
|
||||
ARM_FEATURE_VFP_FP16,
|
||||
ARM_FEATURE_NEON,
|
||||
ARM_FEATURE_DIV,
|
||||
ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
|
||||
ARM_FEATURE_M, /* Microcontroller profile. */
|
||||
ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
|
||||
ARM_FEATURE_THUMB2EE,
|
||||
@ -375,6 +375,8 @@ enum arm_features {
|
||||
ARM_FEATURE_V5,
|
||||
ARM_FEATURE_STRONGARM,
|
||||
ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
|
||||
ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
|
||||
ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
|
||||
};
|
||||
|
||||
static inline int arm_feature(CPUARMState *env, int feature)
|
||||
|
||||
@ -193,7 +193,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
|
||||
set_feature(env, ARM_FEATURE_THUMB2);
|
||||
set_feature(env, ARM_FEATURE_V7);
|
||||
set_feature(env, ARM_FEATURE_M);
|
||||
set_feature(env, ARM_FEATURE_DIV);
|
||||
set_feature(env, ARM_FEATURE_THUMB_DIV);
|
||||
break;
|
||||
case ARM_CPUID_ANY: /* For userspace emulation. */
|
||||
set_feature(env, ARM_FEATURE_V4T);
|
||||
@ -204,10 +204,11 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
|
||||
set_feature(env, ARM_FEATURE_THUMB2);
|
||||
set_feature(env, ARM_FEATURE_VFP);
|
||||
set_feature(env, ARM_FEATURE_VFP3);
|
||||
set_feature(env, ARM_FEATURE_VFP4);
|
||||
set_feature(env, ARM_FEATURE_VFP_FP16);
|
||||
set_feature(env, ARM_FEATURE_NEON);
|
||||
set_feature(env, ARM_FEATURE_THUMB2EE);
|
||||
set_feature(env, ARM_FEATURE_DIV);
|
||||
set_feature(env, ARM_FEATURE_ARM_DIV);
|
||||
set_feature(env, ARM_FEATURE_V7MP);
|
||||
break;
|
||||
case ARM_CPUID_TI915T:
|
||||
@ -261,6 +262,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
|
||||
if (arm_feature(env, ARM_FEATURE_V7)) {
|
||||
set_feature(env, ARM_FEATURE_VAPA);
|
||||
}
|
||||
if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
|
||||
set_feature(env, ARM_FEATURE_THUMB_DIV);
|
||||
}
|
||||
}
|
||||
|
||||
void cpu_reset(CPUARMState *env)
|
||||
@ -471,7 +475,7 @@ static uint32_t cpu_arm_find_by_name(const char *name)
|
||||
|
||||
void cpu_arm_close(CPUARMState *env)
|
||||
{
|
||||
free(env);
|
||||
g_free(env);
|
||||
}
|
||||
|
||||
uint32_t cpsr_read(CPUARMState *env)
|
||||
@ -3039,8 +3043,7 @@ float32 HELPER(rsqrte_f32)(float32 a, CPUState *env)
|
||||
|
||||
val64 = float64_val(f64);
|
||||
|
||||
val = ((val64 >> 63) & 0x80000000)
|
||||
| ((result_exp & 0xff) << 23)
|
||||
val = ((result_exp & 0xff) << 23)
|
||||
| ((val64 >> 29) & 0x7fffff);
|
||||
return make_float32(val);
|
||||
}
|
||||
@ -3082,6 +3085,19 @@ uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env)
|
||||
return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
|
||||
}
|
||||
|
||||
/* VFPv4 fused multiply-accumulate */
|
||||
float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
|
||||
{
|
||||
float_status *fpst = fpstp;
|
||||
return float32_muladd(a, b, c, 0, fpst);
|
||||
}
|
||||
|
||||
float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
|
||||
{
|
||||
float_status *fpst = fpstp;
|
||||
return float64_muladd(a, b, c, 0, fpst);
|
||||
}
|
||||
|
||||
void HELPER(set_teecr)(CPUState *env, uint32_t val)
|
||||
{
|
||||
val &= 1;
|
||||
|
||||
@ -132,6 +132,9 @@ DEF_HELPER_2(vfp_fcvt_f32_to_f16, i32, f32, env)
|
||||
DEF_HELPER_2(neon_fcvt_f16_to_f32, f32, i32, env)
|
||||
DEF_HELPER_2(neon_fcvt_f32_to_f16, i32, f32, env)
|
||||
|
||||
DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, ptr)
|
||||
DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr)
|
||||
|
||||
DEF_HELPER_3(recps_f32, f32, f32, f32, env)
|
||||
DEF_HELPER_3(rsqrts_f32, f32, f32, f32, env)
|
||||
DEF_HELPER_2(recpe_f32, f32, f32, env)
|
||||
|
||||
@ -189,7 +189,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
|
||||
env->vfp.vec_stride = qemu_get_be32(f);
|
||||
|
||||
if (arm_feature(env, ARM_FEATURE_VFP3)) {
|
||||
for (i = 0; i < 16; i++) {
|
||||
for (i = 16; i < 32; i++) {
|
||||
CPU_DoubleU u;
|
||||
u.l.upper = qemu_get_be32(f);
|
||||
u.l.lower = qemu_get_be32(f);
|
||||
|
||||
@ -3141,6 +3141,57 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
|
||||
case 8: /* div: fn / fm */
|
||||
gen_vfp_div(dp);
|
||||
break;
|
||||
case 10: /* VFNMA : fd = muladd(-fd, fn, fm) */
|
||||
case 11: /* VFNMS : fd = muladd(-fd, -fn, fm) */
|
||||
case 12: /* VFMA : fd = muladd( fd, fn, fm) */
|
||||
case 13: /* VFMS : fd = muladd( fd, -fn, fm) */
|
||||
/* These are fused multiply-add, and must be done as one
|
||||
* floating point operation with no rounding between the
|
||||
* multiplication and addition steps.
|
||||
* NB that doing the negations here as separate steps is
|
||||
* correct : an input NaN should come out with its sign bit
|
||||
* flipped if it is a negated-input.
|
||||
*/
|
||||
if (!arm_feature(env, ARM_FEATURE_VFP4)) {
|
||||
return 1;
|
||||
}
|
||||
if (dp) {
|
||||
TCGv_ptr fpst;
|
||||
TCGv_i64 frd;
|
||||
if (op & 1) {
|
||||
/* VFNMS, VFMS */
|
||||
gen_helper_vfp_negd(cpu_F0d, cpu_F0d);
|
||||
}
|
||||
frd = tcg_temp_new_i64();
|
||||
tcg_gen_ld_f64(frd, cpu_env, vfp_reg_offset(dp, rd));
|
||||
if (op & 2) {
|
||||
/* VFNMA, VFNMS */
|
||||
gen_helper_vfp_negd(frd, frd);
|
||||
}
|
||||
fpst = get_fpstatus_ptr(0);
|
||||
gen_helper_vfp_muladdd(cpu_F0d, cpu_F0d,
|
||||
cpu_F1d, frd, fpst);
|
||||
tcg_temp_free_ptr(fpst);
|
||||
tcg_temp_free_i64(frd);
|
||||
} else {
|
||||
TCGv_ptr fpst;
|
||||
TCGv_i32 frd;
|
||||
if (op & 1) {
|
||||
/* VFNMS, VFMS */
|
||||
gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
|
||||
}
|
||||
frd = tcg_temp_new_i32();
|
||||
tcg_gen_ld_f32(frd, cpu_env, vfp_reg_offset(dp, rd));
|
||||
if (op & 2) {
|
||||
gen_helper_vfp_negs(frd, frd);
|
||||
}
|
||||
fpst = get_fpstatus_ptr(0);
|
||||
gen_helper_vfp_muladds(cpu_F0s, cpu_F0s,
|
||||
cpu_F1s, frd, fpst);
|
||||
tcg_temp_free_ptr(fpst);
|
||||
tcg_temp_free_i32(frd);
|
||||
}
|
||||
break;
|
||||
case 14: /* fconst */
|
||||
if (!arm_feature(env, ARM_FEATURE_VFP3))
|
||||
return 1;
|
||||
@ -4417,6 +4468,7 @@ static void gen_neon_narrow_op(int op, int u, int size, TCGv dest, TCGv_i64 src)
|
||||
#define NEON_3R_VPMIN 21
|
||||
#define NEON_3R_VQDMULH_VQRDMULH 22
|
||||
#define NEON_3R_VPADD 23
|
||||
#define NEON_3R_VFM 25 /* VFMA, VFMS : float fused multiply-add */
|
||||
#define NEON_3R_FLOAT_ARITH 26 /* float VADD, VSUB, VPADD, VABD */
|
||||
#define NEON_3R_FLOAT_MULTIPLY 27 /* float VMLA, VMLS, VMUL */
|
||||
#define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */
|
||||
@ -4449,6 +4501,7 @@ static const uint8_t neon_3r_sizes[] = {
|
||||
[NEON_3R_VPMIN] = 0x7,
|
||||
[NEON_3R_VQDMULH_VQRDMULH] = 0x6,
|
||||
[NEON_3R_VPADD] = 0x7,
|
||||
[NEON_3R_VFM] = 0x5, /* size bit 1 encodes op */
|
||||
[NEON_3R_FLOAT_ARITH] = 0x5, /* size bit 1 encodes op */
|
||||
[NEON_3R_FLOAT_MULTIPLY] = 0x5, /* size bit 1 encodes op */
|
||||
[NEON_3R_FLOAT_CMP] = 0x5, /* size bit 1 encodes op */
|
||||
@ -4726,6 +4779,11 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
case NEON_3R_VFM:
|
||||
if (!arm_feature(env, ARM_FEATURE_VFP4) || u) {
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
@ -5006,6 +5064,20 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
|
||||
else
|
||||
gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env);
|
||||
break;
|
||||
case NEON_3R_VFM:
|
||||
{
|
||||
/* VFMA, VFMS: fused multiply-add */
|
||||
TCGv_ptr fpstatus = get_fpstatus_ptr(1);
|
||||
TCGv_i32 tmp3 = neon_load_reg(rd, pass);
|
||||
if (size) {
|
||||
/* VFMS */
|
||||
gen_helper_vfp_negs(tmp, tmp);
|
||||
}
|
||||
gen_helper_vfp_muladds(tmp, tmp, tmp2, tmp3, fpstatus);
|
||||
tcg_temp_free_i32(tmp3);
|
||||
tcg_temp_free_ptr(fpstatus);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
abort();
|
||||
}
|
||||
@ -7569,11 +7641,16 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
|
||||
}
|
||||
break;
|
||||
case 2: /* Multiplies (Type 3). */
|
||||
tmp = load_reg(s, rm);
|
||||
tmp2 = load_reg(s, rs);
|
||||
if (insn & (1 << 20)) {
|
||||
switch ((insn >> 20) & 0x7) {
|
||||
case 5:
|
||||
if (((insn >> 6) ^ (insn >> 7)) & 1) {
|
||||
/* op2 not 00x or 11x : UNDEF */
|
||||
goto illegal_op;
|
||||
}
|
||||
/* Signed multiply most significant [accumulate].
|
||||
(SMMUL, SMMLA, SMMLS) */
|
||||
tmp = load_reg(s, rm);
|
||||
tmp2 = load_reg(s, rs);
|
||||
tmp64 = gen_muls_i64_i32(tmp, tmp2);
|
||||
|
||||
if (rd != 15) {
|
||||
@ -7592,7 +7669,15 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
|
||||
tcg_gen_trunc_i64_i32(tmp, tmp64);
|
||||
tcg_temp_free_i64(tmp64);
|
||||
store_reg(s, rn, tmp);
|
||||
} else {
|
||||
break;
|
||||
case 0:
|
||||
case 4:
|
||||
/* SMLAD, SMUAD, SMLSD, SMUSD, SMLALD, SMLSLD */
|
||||
if (insn & (1 << 7)) {
|
||||
goto illegal_op;
|
||||
}
|
||||
tmp = load_reg(s, rm);
|
||||
tmp2 = load_reg(s, rs);
|
||||
if (insn & (1 << 5))
|
||||
gen_swap_half(tmp2);
|
||||
gen_smul_dual(tmp, tmp2);
|
||||
@ -7625,6 +7710,28 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
|
||||
}
|
||||
store_reg(s, rn, tmp);
|
||||
}
|
||||
break;
|
||||
case 1:
|
||||
case 3:
|
||||
/* SDIV, UDIV */
|
||||
if (!arm_feature(env, ARM_FEATURE_ARM_DIV)) {
|
||||
goto illegal_op;
|
||||
}
|
||||
if (((insn >> 5) & 7) || (rd != 15)) {
|
||||
goto illegal_op;
|
||||
}
|
||||
tmp = load_reg(s, rm);
|
||||
tmp2 = load_reg(s, rs);
|
||||
if (insn & (1 << 21)) {
|
||||
gen_helper_udiv(tmp, tmp, tmp2);
|
||||
} else {
|
||||
gen_helper_sdiv(tmp, tmp, tmp2);
|
||||
}
|
||||
tcg_temp_free_i32(tmp2);
|
||||
store_reg(s, rn, tmp);
|
||||
break;
|
||||
default:
|
||||
goto illegal_op;
|
||||
}
|
||||
break;
|
||||
case 3:
|
||||
@ -8497,8 +8604,9 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
|
||||
tmp2 = load_reg(s, rm);
|
||||
if ((op & 0x50) == 0x10) {
|
||||
/* sdiv, udiv */
|
||||
if (!arm_feature(env, ARM_FEATURE_DIV))
|
||||
if (!arm_feature(env, ARM_FEATURE_THUMB_DIV)) {
|
||||
goto illegal_op;
|
||||
}
|
||||
if (op & 0x20)
|
||||
gen_helper_udiv(tmp, tmp, tmp2);
|
||||
else
|
||||
|
||||
Loading…
Reference in New Issue
Block a user