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alpha: fix lit sign
according to the alpha arch reference, the literal field of an operate instruction is unsigned: If bit <12> of the instruction is 1, an 8-bit zero-extended literal constant is formed by bits <20:13> of the instruction. The l teral is interpreted as a positive integer bet ween 0 and 255 and is zero-extended to 64 bits. This patch fixes the mis-interpretation of the literal field. (Tristan Gingold) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5211 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -351,7 +351,7 @@ static always_inline void gen_fbcond (DisasContext *ctx,
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static always_inline void gen_arith2 (DisasContext *ctx,
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void (*gen_arith_op)(void),
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int rb, int rc, int islit, int8_t lit)
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int rb, int rc, int islit, uint8_t lit)
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{
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if (islit)
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tcg_gen_movi_i64(cpu_T[0], lit);
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@ -367,7 +367,7 @@ static always_inline void gen_arith2 (DisasContext *ctx,
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static always_inline void gen_arith3 (DisasContext *ctx,
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void (*gen_arith_op)(void),
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int ra, int rb, int rc,
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int islit, int8_t lit)
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int islit, uint8_t lit)
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{
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if (ra != 31)
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tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
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@ -387,7 +387,7 @@ static always_inline void gen_arith3 (DisasContext *ctx,
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static always_inline void gen_cmov (DisasContext *ctx,
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void (*gen_test_op)(void),
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int ra, int rb, int rc,
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int islit, int8_t lit)
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int islit, uint8_t lit)
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{
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if (ra != 31)
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tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
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