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target/i386/tcg: Enable page walking from MMIO memory
CXL emulation of interleave requires read and write hooks due to
requirement for subpage granularity. The Linux kernel stack now enables
using this memory as conventional memory in a separate NUMA node. If a
process is deliberately forced to run from that node
$ numactl --membind=1 ls
the page table walk on i386 fails.
Useful part of backtrace:
(cpu=cpu@entry=0x555556fd9000, fmt=fmt@entry=0x555555fe3378 "cpu_io_recompile: could not find TB for pc=%p")
at ../../cpu-target.c:359
(retaddr=0, addr=19595792376, attrs=..., xlat=<optimized out>, cpu=0x555556fd9000, out_offset=<synthetic pointer>)
at ../../accel/tcg/cputlb.c:1339
(cpu=0x555556fd9000, full=0x7fffee0d96e0, ret_be=ret_be@entry=0, addr=19595792376, size=size@entry=8, mmu_idx=4, type=MMU_DATA_LOAD, ra=0) at ../../accel/tcg/cputlb.c:2030
(cpu=cpu@entry=0x555556fd9000, p=p@entry=0x7ffff56fddc0, mmu_idx=<optimized out>, type=type@entry=MMU_DATA_LOAD, memop=<optimized out>, ra=ra@entry=0) at ../../accel/tcg/cputlb.c:2356
(cpu=cpu@entry=0x555556fd9000, addr=addr@entry=19595792376, oi=oi@entry=52, ra=ra@entry=0, access_type=access_type@entry=MMU_DATA_LOAD) at ../../accel/tcg/cputlb.c:2439
at ../../accel/tcg/ldst_common.c.inc:301
at ../../target/i386/tcg/sysemu/excp_helper.c:173
(err=0x7ffff56fdf80, out=0x7ffff56fdf70, mmu_idx=0, access_type=MMU_INST_FETCH, addr=18446744072116178925, env=0x555556fdb7c0)
at ../../target/i386/tcg/sysemu/excp_helper.c:578
(cs=0x555556fd9000, addr=18446744072116178925, size=<optimized out>, access_type=MMU_INST_FETCH, mmu_idx=0, probe=<optimized out>, retaddr=0) at ../../target/i386/tcg/sysemu/excp_helper.c:604
Avoid this by plumbing the address all the way down from
x86_cpu_tlb_fill() where is available as retaddr to the actual accessors
which provide it to probe_access_full() which already handles MMIO accesses.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2180
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2220
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Gregory Price <gregory.price@memverge.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-ID: <20240307155304.31241-2-Jonathan.Cameron@huawei.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Gregory Price
Philippe Mathieu-Daudé
parent
096ae430a7
commit
9dab7bbb01
@ -59,14 +59,14 @@ typedef struct PTETranslate {
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hwaddr gaddr;
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} PTETranslate;
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static bool ptw_translate(PTETranslate *inout, hwaddr addr)
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static bool ptw_translate(PTETranslate *inout, hwaddr addr, uint64_t ra)
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{
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CPUTLBEntryFull *full;
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int flags;
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inout->gaddr = addr;
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flags = probe_access_full(inout->env, addr, 0, MMU_DATA_STORE,
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inout->ptw_idx, true, &inout->haddr, &full, 0);
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inout->ptw_idx, true, &inout->haddr, &full, ra);
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if (unlikely(flags & TLB_INVALID_MASK)) {
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TranslateFault *err = inout->err;
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@ -82,20 +82,20 @@ static bool ptw_translate(PTETranslate *inout, hwaddr addr)
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return true;
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}
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static inline uint32_t ptw_ldl(const PTETranslate *in)
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static inline uint32_t ptw_ldl(const PTETranslate *in, uint64_t ra)
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{
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if (likely(in->haddr)) {
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return ldl_p(in->haddr);
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}
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return cpu_ldl_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, 0);
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return cpu_ldl_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra);
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}
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static inline uint64_t ptw_ldq(const PTETranslate *in)
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static inline uint64_t ptw_ldq(const PTETranslate *in, uint64_t ra)
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{
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if (likely(in->haddr)) {
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return ldq_p(in->haddr);
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}
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return cpu_ldq_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, 0);
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return cpu_ldq_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra);
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}
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/*
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@ -132,7 +132,8 @@ static inline bool ptw_setl(const PTETranslate *in, uint32_t old, uint32_t set)
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}
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static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
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TranslateResult *out, TranslateFault *err)
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TranslateResult *out, TranslateFault *err,
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uint64_t ra)
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{
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const target_ulong addr = in->addr;
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const int pg_mode = in->pg_mode;
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@ -164,11 +165,11 @@ static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
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* Page table level 5
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*/
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pte_addr = (in->cr3 & ~0xfff) + (((addr >> 48) & 0x1ff) << 3);
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if (!ptw_translate(&pte_trans, pte_addr)) {
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if (!ptw_translate(&pte_trans, pte_addr, ra)) {
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return false;
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}
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restart_5:
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pte = ptw_ldq(&pte_trans);
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pte = ptw_ldq(&pte_trans, ra);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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@ -188,11 +189,11 @@ static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
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* Page table level 4
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*/
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pte_addr = (pte & PG_ADDRESS_MASK) + (((addr >> 39) & 0x1ff) << 3);
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if (!ptw_translate(&pte_trans, pte_addr)) {
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if (!ptw_translate(&pte_trans, pte_addr, ra)) {
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return false;
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}
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restart_4:
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pte = ptw_ldq(&pte_trans);
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pte = ptw_ldq(&pte_trans, ra);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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@ -208,11 +209,11 @@ static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
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* Page table level 3
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*/
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pte_addr = (pte & PG_ADDRESS_MASK) + (((addr >> 30) & 0x1ff) << 3);
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if (!ptw_translate(&pte_trans, pte_addr)) {
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if (!ptw_translate(&pte_trans, pte_addr, ra)) {
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return false;
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}
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restart_3_lma:
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pte = ptw_ldq(&pte_trans);
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pte = ptw_ldq(&pte_trans, ra);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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@ -235,12 +236,12 @@ static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
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* Page table level 3
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*/
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pte_addr = (in->cr3 & 0xffffffe0ULL) + ((addr >> 27) & 0x18);
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if (!ptw_translate(&pte_trans, pte_addr)) {
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if (!ptw_translate(&pte_trans, pte_addr, ra)) {
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return false;
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}
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rsvd_mask |= PG_HI_USER_MASK;
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restart_3_nolma:
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pte = ptw_ldq(&pte_trans);
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pte = ptw_ldq(&pte_trans, ra);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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@ -257,11 +258,11 @@ static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
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* Page table level 2
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*/
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pte_addr = (pte & PG_ADDRESS_MASK) + (((addr >> 21) & 0x1ff) << 3);
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if (!ptw_translate(&pte_trans, pte_addr)) {
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if (!ptw_translate(&pte_trans, pte_addr, ra)) {
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return false;
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}
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restart_2_pae:
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pte = ptw_ldq(&pte_trans);
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pte = ptw_ldq(&pte_trans, ra);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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@ -283,10 +284,10 @@ static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
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* Page table level 1
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*/
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pte_addr = (pte & PG_ADDRESS_MASK) + (((addr >> 12) & 0x1ff) << 3);
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if (!ptw_translate(&pte_trans, pte_addr)) {
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if (!ptw_translate(&pte_trans, pte_addr, ra)) {
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return false;
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}
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pte = ptw_ldq(&pte_trans);
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pte = ptw_ldq(&pte_trans, ra);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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@ -301,11 +302,11 @@ static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
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* Page table level 2
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*/
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pte_addr = (in->cr3 & 0xfffff000ULL) + ((addr >> 20) & 0xffc);
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if (!ptw_translate(&pte_trans, pte_addr)) {
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if (!ptw_translate(&pte_trans, pte_addr, ra)) {
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return false;
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}
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restart_2_nopae:
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pte = ptw_ldl(&pte_trans);
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pte = ptw_ldl(&pte_trans, ra);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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@ -330,10 +331,10 @@ static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
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* Page table level 1
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*/
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pte_addr = (pte & ~0xfffu) + ((addr >> 10) & 0xffc);
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if (!ptw_translate(&pte_trans, pte_addr)) {
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if (!ptw_translate(&pte_trans, pte_addr, ra)) {
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return false;
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}
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pte = ptw_ldl(&pte_trans);
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pte = ptw_ldl(&pte_trans, ra);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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@ -526,7 +527,8 @@ static G_NORETURN void raise_stage2(CPUX86State *env, TranslateFault *err,
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static bool get_physical_address(CPUX86State *env, vaddr addr,
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MMUAccessType access_type, int mmu_idx,
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TranslateResult *out, TranslateFault *err)
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TranslateResult *out, TranslateFault *err,
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uint64_t ra)
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{
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TranslateParams in;
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bool use_stage2 = env->hflags2 & HF2_NPT_MASK;
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@ -546,7 +548,7 @@ static bool get_physical_address(CPUX86State *env, vaddr addr,
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env->nested_pg_mode & PG_MODE_LMA ? MMU_USER64_IDX : MMU_USER32_IDX;
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in.ptw_idx = MMU_PHYS_IDX;
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if (!mmu_translate(env, &in, out, err)) {
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if (!mmu_translate(env, &in, out, err, ra)) {
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err->stage2 = S2_GPA;
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return false;
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}
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@ -577,7 +579,7 @@ static bool get_physical_address(CPUX86State *env, vaddr addr,
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return false;
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}
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}
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return mmu_translate(env, &in, out, err);
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return mmu_translate(env, &in, out, err, ra);
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}
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break;
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}
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@ -597,7 +599,8 @@ bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
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TranslateResult out;
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TranslateFault err;
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if (get_physical_address(env, addr, access_type, mmu_idx, &out, &err)) {
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if (get_physical_address(env, addr, access_type, mmu_idx, &out, &err,
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retaddr)) {
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/*
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* Even if 4MB pages, we map only one 4KB page in the cache to
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* avoid filling it too fast.
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