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hw/pcie: Introduce a base class for PCI Express Root Ports
The 'base' PCI Express Root Port includes the common code to be re-used for all Root Ports implementations. Most of the code was taken from the current implementation of Intel's IOH 3420 Root Port. Signed-off-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Marcel Apfelbaum
Michael S. Tsirkin
parent
04eb6247eb
commit
9d5154d753
@ -108,6 +108,7 @@ CONFIG_FSL_IMX25=y
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CONFIG_IMX_I2C=y
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CONFIG_PCIE_PORT=y
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CONFIG_XIO3130=y
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CONFIG_IOH3420=y
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CONFIG_I82801B11=y
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@ -51,6 +51,7 @@ CONFIG_PVPANIC=y
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CONFIG_MEM_HOTPLUG=y
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CONFIG_NVDIMM=y
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CONFIG_ACPI_NVDIMM=y
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CONFIG_PCIE_PORT=y
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CONFIG_XIO3130=y
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CONFIG_IOH3420=y
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CONFIG_I82801B11=y
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@ -51,6 +51,7 @@ CONFIG_PVPANIC=y
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CONFIG_MEM_HOTPLUG=y
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CONFIG_NVDIMM=y
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CONFIG_ACPI_NVDIMM=y
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CONFIG_PCIE_PORT=y
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CONFIG_XIO3130=y
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CONFIG_IOH3420=y
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CONFIG_I82801B11=y
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@ -1,5 +1,6 @@
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common-obj-y += pci_bridge_dev.o
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common-obj-y += pci_expander_bridge.o
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common-obj-$(CONFIG_PCIE_PORT) += pcie_root_port.o
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common-obj-$(CONFIG_XIO3130) += xio3130_upstream.o xio3130_downstream.o
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common-obj-$(CONFIG_IOH3420) += ioh3420.o
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common-obj-$(CONFIG_I82801B11) += i82801b11.o
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171
hw/pci-bridge/pcie_root_port.c
Normal file
171
hw/pci-bridge/pcie_root_port.c
Normal file
@ -0,0 +1,171 @@
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/*
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* Base class for PCI Express Root Ports
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*
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* Copyright (C) 2017 Red Hat Inc
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*
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* Authors:
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* Marcel Apfelbaum <marcel@redhat.com>
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*
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* Most of the code was migrated from hw/pci-bridge/ioh3420.
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/pci/pcie_port.h"
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static void rp_aer_vector_update(PCIDevice *d)
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{
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PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);
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if (rpc->aer_vector) {
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pcie_aer_root_set_vector(d, rpc->aer_vector(d));
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}
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}
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static void rp_write_config(PCIDevice *d, uint32_t address,
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uint32_t val, int len)
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{
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uint32_t root_cmd =
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pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND);
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pci_bridge_write_config(d, address, val, len);
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rp_aer_vector_update(d);
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pcie_cap_slot_write_config(d, address, val, len);
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pcie_aer_write_config(d, address, val, len);
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pcie_aer_root_write_config(d, address, val, len, root_cmd);
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}
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static void rp_reset(DeviceState *qdev)
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{
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PCIDevice *d = PCI_DEVICE(qdev);
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rp_aer_vector_update(d);
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pcie_cap_root_reset(d);
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pcie_cap_deverr_reset(d);
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pcie_cap_slot_reset(d);
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pcie_cap_arifwd_reset(d);
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pcie_aer_root_reset(d);
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pci_bridge_reset(qdev);
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pci_bridge_disable_base_limit(d);
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}
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static void rp_realize(PCIDevice *d, Error **errp)
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{
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PCIEPort *p = PCIE_PORT(d);
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PCIESlot *s = PCIE_SLOT(d);
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PCIDeviceClass *dc = PCI_DEVICE_GET_CLASS(d);
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PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);
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int rc;
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Error *local_err = NULL;
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pci_config_set_interrupt_pin(d->config, 1);
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pci_bridge_initfn(d, TYPE_PCIE_BUS);
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pcie_port_init_reg(d);
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rc = pci_bridge_ssvid_init(d, rpc->ssvid_offset, dc->vendor_id, rpc->ssid);
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if (rc < 0) {
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error_setg(errp, "Can't init SSV ID, error %d", rc);
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goto err_bridge;
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}
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if (rpc->interrupts_init) {
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rc = rpc->interrupts_init(d, &local_err);
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if (rc < 0) {
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error_propagate(errp, local_err);
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goto err_bridge;
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}
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}
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rc = pcie_cap_init(d, rpc->exp_offset, PCI_EXP_TYPE_ROOT_PORT, p->port);
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if (rc < 0) {
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error_setg(errp, "Can't add Root Port capability, error %d", rc);
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goto err_int;
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}
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pcie_cap_arifwd_init(d);
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pcie_cap_deverr_init(d);
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pcie_cap_slot_init(d, s->slot);
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pcie_cap_root_init(d);
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pcie_chassis_create(s->chassis);
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rc = pcie_chassis_add_slot(s);
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if (rc < 0) {
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error_setg(errp, "Can't add chassis slot, error %d", rc);
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goto err_pcie_cap;
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}
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rc = pcie_aer_init(d, PCI_ERR_VER, rpc->aer_offset,
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PCI_ERR_SIZEOF, &local_err);
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if (rc < 0) {
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error_propagate(errp, local_err);
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goto err;
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}
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pcie_aer_root_init(d);
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rp_aer_vector_update(d);
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return;
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err:
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pcie_chassis_del_slot(s);
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err_pcie_cap:
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pcie_cap_exit(d);
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err_int:
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if (rpc->interrupts_uninit) {
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rpc->interrupts_uninit(d);
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}
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err_bridge:
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pci_bridge_exitfn(d);
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}
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static void rp_exit(PCIDevice *d)
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{
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PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);
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PCIESlot *s = PCIE_SLOT(d);
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pcie_aer_exit(d);
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pcie_chassis_del_slot(s);
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pcie_cap_exit(d);
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if (rpc->interrupts_uninit) {
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rpc->interrupts_uninit(d);
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}
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pci_bridge_exitfn(d);
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}
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static Property rp_props[] = {
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DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,
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QEMU_PCIE_SLTCAP_PCP_BITNR, true),
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DEFINE_PROP_END_OF_LIST()
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};
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static void rp_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->is_express = 1;
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k->is_bridge = 1;
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k->config_write = rp_write_config;
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k->realize = rp_realize;
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k->exit = rp_exit;
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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dc->reset = rp_reset;
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dc->props = rp_props;
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}
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static const TypeInfo rp_info = {
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.name = TYPE_PCIE_ROOT_PORT,
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.parent = TYPE_PCIE_SLOT,
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.class_init = rp_class_init,
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.abstract = true,
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.class_size = sizeof(PCIERootPortClass),
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};
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static void rp_register_types(void)
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{
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type_register_static(&rp_info);
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}
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type_init(rp_register_types)
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@ -57,4 +57,23 @@ PCIESlot *pcie_chassis_find_slot(uint8_t chassis, uint16_t slot);
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int pcie_chassis_add_slot(struct PCIESlot *slot);
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void pcie_chassis_del_slot(PCIESlot *s);
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#define TYPE_PCIE_ROOT_PORT "pcie-root-port-base"
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#define PCIE_ROOT_PORT_CLASS(klass) \
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OBJECT_CLASS_CHECK(PCIERootPortClass, (klass), TYPE_PCIE_ROOT_PORT)
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#define PCIE_ROOT_PORT_GET_CLASS(obj) \
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OBJECT_GET_CLASS(PCIERootPortClass, (obj), TYPE_PCIE_ROOT_PORT)
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typedef struct PCIERootPortClass {
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PCIDeviceClass parent_class;
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uint8_t (*aer_vector)(const PCIDevice *dev);
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int (*interrupts_init)(PCIDevice *dev, Error **errp);
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void (*interrupts_uninit)(PCIDevice *dev);
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int exp_offset;
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int aer_offset;
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int ssvid_offset;
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int ssid;
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} PCIERootPortClass;
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#endif /* QEMU_PCIE_PORT_H */
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