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arm11mpcore: Split off RealView MPCore
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Andreas Färber
parent
7b960dc37d
commit
9c219b7be6
@ -1,4 +1,5 @@
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obj-$(CONFIG_ARM11MPCORE) += arm11mpcore.o
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obj-$(CONFIG_REALVIEW) += realview_mpcore.o
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obj-$(CONFIG_A9MPCORE) += a9mpcore.o
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obj-$(CONFIG_A15MPCORE) += a15mpcore.o
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obj-$(CONFIG_ICC_BUS) += icc_bus.o
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@ -134,126 +134,6 @@ static void mpcore_priv_initfn(Object *obj)
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qdev_set_parent_bus(DEVICE(&s->wdtimer), sysbus_get_default());
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}
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#define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore"
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#define REALVIEW_MPCORE_RIRQ(obj) \
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OBJECT_CHECK(mpcore_rirq_state, (obj), TYPE_REALVIEW_MPCORE_RIRQ)
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/* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ
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controllers. The output of these, plus some of the raw input lines
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are fed into a single SMP-aware interrupt controller on the CPU. */
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typedef struct {
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SysBusDevice parent_obj;
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qemu_irq cpuic[32];
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qemu_irq rvic[4][64];
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uint32_t num_cpu;
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ARM11MPCorePriveState priv;
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RealViewGICState gic[4];
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} mpcore_rirq_state;
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/* Map baseboard IRQs onto CPU IRQ lines. */
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static const int mpcore_irq_map[32] = {
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-1, -1, -1, -1, 1, 2, -1, -1,
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-1, -1, 6, -1, 4, 5, -1, -1,
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-1, 14, 15, 0, 7, 8, -1, -1,
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-1, -1, -1, -1, 9, 3, -1, -1,
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};
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static void mpcore_rirq_set_irq(void *opaque, int irq, int level)
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{
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mpcore_rirq_state *s = (mpcore_rirq_state *)opaque;
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int i;
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for (i = 0; i < 4; i++) {
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qemu_set_irq(s->rvic[i][irq], level);
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}
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if (irq < 32) {
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irq = mpcore_irq_map[irq];
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if (irq >= 0) {
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qemu_set_irq(s->cpuic[irq], level);
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}
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}
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}
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static void realview_mpcore_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(dev);
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DeviceState *priv = DEVICE(&s->priv);
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DeviceState *gic;
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SysBusDevice *gicbusdev;
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Error *err = NULL;
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int n;
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int i;
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qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
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object_property_set_bool(OBJECT(&s->priv), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->priv));
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for (i = 0; i < 32; i++) {
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s->cpuic[i] = qdev_get_gpio_in(priv, i);
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}
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/* ??? IRQ routing is hardcoded to "normal" mode. */
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for (n = 0; n < 4; n++) {
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object_property_set_bool(OBJECT(&s->gic[n]), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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gic = DEVICE(&s->gic[n]);
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gicbusdev = SYS_BUS_DEVICE(&s->gic[n]);
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sysbus_mmio_map(gicbusdev, 0, 0x10040000 + n * 0x10000);
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sysbus_connect_irq(gicbusdev, 0, s->cpuic[10 + n]);
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for (i = 0; i < 64; i++) {
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s->rvic[n][i] = qdev_get_gpio_in(gic, i);
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}
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}
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qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64);
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}
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static void mpcore_rirq_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(obj);
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SysBusDevice *privbusdev;
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int i;
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object_initialize(&s->priv, sizeof(s->priv), TYPE_ARM11MPCORE_PRIV);
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qdev_set_parent_bus(DEVICE(&s->priv), sysbus_get_default());
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privbusdev = SYS_BUS_DEVICE(&s->priv);
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sysbus_init_mmio(sbd, sysbus_mmio_get_region(privbusdev, 0));
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for (i = 0; i < 4; i++) {
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object_initialize(&s->gic[i], sizeof(s->gic[i]), TYPE_REALVIEW_GIC);
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qdev_set_parent_bus(DEVICE(&s->gic[i]), sysbus_get_default());
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}
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}
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static Property mpcore_rirq_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void mpcore_rirq_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = realview_mpcore_realize;
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dc->props = mpcore_rirq_properties;
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}
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static const TypeInfo mpcore_rirq_info = {
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.name = TYPE_REALVIEW_MPCORE_RIRQ,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(mpcore_rirq_state),
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.instance_init = mpcore_rirq_init,
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.class_init = mpcore_rirq_class_init,
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};
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static Property mpcore_priv_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1),
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/* The ARM11 MPCORE TRM says the on-chip controller may have
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@ -286,7 +166,6 @@ static const TypeInfo mpcore_priv_info = {
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static void arm11mpcore_register_types(void)
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{
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type_register_static(&mpcore_rirq_info);
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type_register_static(&mpcore_priv_info);
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}
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139
hw/cpu/realview_mpcore.c
Normal file
139
hw/cpu/realview_mpcore.c
Normal file
@ -0,0 +1,139 @@
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/*
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* RealView ARM11MPCore internal peripheral emulation
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Copyright (c) 2013 SUSE LINUX Products GmbH
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* Written by Paul Brook and Andreas Färber
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*
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* This code is licensed under the GPL.
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*/
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#include "hw/cpu/arm11mpcore.h"
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#include "hw/intc/realview_gic.h"
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#define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore"
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#define REALVIEW_MPCORE_RIRQ(obj) \
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OBJECT_CHECK(mpcore_rirq_state, (obj), TYPE_REALVIEW_MPCORE_RIRQ)
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/* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ
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controllers. The output of these, plus some of the raw input lines
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are fed into a single SMP-aware interrupt controller on the CPU. */
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typedef struct {
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SysBusDevice parent_obj;
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qemu_irq cpuic[32];
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qemu_irq rvic[4][64];
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uint32_t num_cpu;
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ARM11MPCorePriveState priv;
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RealViewGICState gic[4];
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} mpcore_rirq_state;
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/* Map baseboard IRQs onto CPU IRQ lines. */
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static const int mpcore_irq_map[32] = {
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-1, -1, -1, -1, 1, 2, -1, -1,
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-1, -1, 6, -1, 4, 5, -1, -1,
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-1, 14, 15, 0, 7, 8, -1, -1,
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-1, -1, -1, -1, 9, 3, -1, -1,
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};
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static void mpcore_rirq_set_irq(void *opaque, int irq, int level)
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{
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mpcore_rirq_state *s = (mpcore_rirq_state *)opaque;
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int i;
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for (i = 0; i < 4; i++) {
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qemu_set_irq(s->rvic[i][irq], level);
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}
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if (irq < 32) {
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irq = mpcore_irq_map[irq];
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if (irq >= 0) {
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qemu_set_irq(s->cpuic[irq], level);
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}
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}
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}
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static void realview_mpcore_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(dev);
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DeviceState *priv = DEVICE(&s->priv);
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DeviceState *gic;
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SysBusDevice *gicbusdev;
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Error *err = NULL;
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int n;
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int i;
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qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
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object_property_set_bool(OBJECT(&s->priv), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->priv));
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for (i = 0; i < 32; i++) {
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s->cpuic[i] = qdev_get_gpio_in(priv, i);
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}
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/* ??? IRQ routing is hardcoded to "normal" mode. */
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for (n = 0; n < 4; n++) {
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object_property_set_bool(OBJECT(&s->gic[n]), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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gic = DEVICE(&s->gic[n]);
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gicbusdev = SYS_BUS_DEVICE(&s->gic[n]);
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sysbus_mmio_map(gicbusdev, 0, 0x10040000 + n * 0x10000);
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sysbus_connect_irq(gicbusdev, 0, s->cpuic[10 + n]);
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for (i = 0; i < 64; i++) {
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s->rvic[n][i] = qdev_get_gpio_in(gic, i);
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}
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}
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qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64);
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}
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static void mpcore_rirq_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(obj);
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SysBusDevice *privbusdev;
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int i;
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object_initialize(&s->priv, sizeof(s->priv), TYPE_ARM11MPCORE_PRIV);
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qdev_set_parent_bus(DEVICE(&s->priv), sysbus_get_default());
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privbusdev = SYS_BUS_DEVICE(&s->priv);
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sysbus_init_mmio(sbd, sysbus_mmio_get_region(privbusdev, 0));
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for (i = 0; i < 4; i++) {
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object_initialize(&s->gic[i], sizeof(s->gic[i]), TYPE_REALVIEW_GIC);
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qdev_set_parent_bus(DEVICE(&s->gic[i]), sysbus_get_default());
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}
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}
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static Property mpcore_rirq_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void mpcore_rirq_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = realview_mpcore_realize;
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dc->props = mpcore_rirq_properties;
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}
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static const TypeInfo mpcore_rirq_info = {
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.name = TYPE_REALVIEW_MPCORE_RIRQ,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(mpcore_rirq_state),
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.instance_init = mpcore_rirq_init,
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.class_init = mpcore_rirq_class_init,
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};
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static void realview_mpcore_register_types(void)
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{
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type_register_static(&mpcore_rirq_info);
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}
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type_init(realview_mpcore_register_types)
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