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hw/arm/xilinx_zynq: Fix IRQ/FIQ routing

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Fix the system bus interrupt line to CPU core assignment.

Fixes: ddcf58e044 ("hw/arm/xilinx_zynq: Support up to two CPU cores")
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240610052906.4432-1-sebastian.huber@embedded-brains.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Sebastian Huber 2024-06-18 16:22:21 +01:00 committed by Peter Maydell
parent 7175a562f1
commit 9b113a09ff
1 changed files with 3 additions and 2 deletions
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5
hw/arm/xilinx_zynq.c
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@ -252,10 +252,11 @@ static void zynq_init(MachineState *machine)
zynq_binfo.gic_cpu_if_addr = MPCORE_PERIPHBASE + 0x100;
sysbus_create_varargs("l2x0", MPCORE_PERIPHBASE + 0x2000, NULL);
for (n = 0; n < smp_cpus; n++) {
/* See "hw/intc/arm_gic.h" for the IRQ line association */
DeviceState *cpudev = DEVICE(zynq_machine->cpu[n]);
sysbus_connect_irq(busdev, (2 * n) + 0,
sysbus_connect_irq(busdev, n,
qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
sysbus_connect_irq(busdev, (2 * n) + 1,
sysbus_connect_irq(busdev, smp_cpus + n,
qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
}