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ppc/pnv: Add models for POWER8 PHB3 PCIe Host bridge

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This is a model of the PCIe Host Bridge (PHB3) found on a POWER8
processor. It includes the PowerBus logic interface (PBCQ), IOMMU
support, a single PCIe Gen.3 Root Complex, and support for MSI and LSI
interrupt sources as found on a POWER8 system using the XICS interrupt
controller.

The POWER8 processor comes in different flavors: Venice, Murano,
Naple, each having a different number of PHBs. To make things simpler,
the models provides 3 PHB3 per chip. Some platforms, like the
Firestone, can also couple PHBs on the first chip to provide more
bandwidth but this is too specific to model in QEMU.

XICS requires some adjustment to support the PHB3 MSI. The changes are
provided here but they could be decoupled in prereq patches.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20200127144506.11132-3-clg@kaod.org>
[dwg: Use device_class_set_props()]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Cédric Le Goater 2020-01-27 15:45:06 +01:00 committed by David Gibson
parent 4f9924c4d4
commit 9ae1329ee2
11 changed files with 2614 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
hw/intc/xics.c
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@ -217,7 +217,7 @@ void icp_eoi(ICPState *icp, uint32_t xirr)
}
}
static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
{
ICPState *icp = xics_icp_get(ics->xics, server);
@ -512,8 +512,14 @@ void ics_write_xive(ICSState *ics, int srcno, int server,
static void ics_reject(ICSState *ics, uint32_t nr)
{
ICSStateClass *isc = ICS_GET_CLASS(ics);
ICSIRQState *irq = ics->irqs + nr - ics->offset;
if (isc->reject) {
isc->reject(ics, nr);
return;
}
trace_xics_ics_reject(nr, nr - ics->offset);
if (irq->flags & XICS_FLAGS_IRQ_MSI) {
irq->status |= XICS_STATUS_REJECTED;
@ -524,8 +530,14 @@ static void ics_reject(ICSState *ics, uint32_t nr)
void ics_resend(ICSState *ics)
{
ICSStateClass *isc = ICS_GET_CLASS(ics);
int i;
if (isc->resend) {
isc->resend(ics);
return;
}
for (i = 0; i < ics->nr_irqs; i++) {
/* FIXME: filter by server#? */
if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {

1
hw/pci-host/Makefile.objs
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@ -21,3 +21,4 @@ common-obj-$(CONFIG_PCI_EXPRESS_XILINX) += xilinx-pcie.o
common-obj-$(CONFIG_PCI_EXPRESS_DESIGNWARE) += designware.o
obj-$(CONFIG_POWERNV) += pnv_phb4.o pnv_phb4_pec.o
obj-$(CONFIG_POWERNV) += pnv_phb3.o pnv_phb3_msi.o pnv_phb3_pbcq.o

1195
hw/pci-host/pnv_phb3.c Normal file
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File diff suppressed because it is too large Load Diff

349
hw/pci-host/pnv_phb3_msi.c Normal file
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@ -0,0 +1,349 @@
/*
* QEMU PowerPC PowerNV (POWER8) PHB3 model
*
* Copyright (c) 2014-2020, IBM Corporation.
*
* This code is licensed under the GPL version 2 or later. See the
* COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "hw/pci-host/pnv_phb3_regs.h"
#include "hw/pci-host/pnv_phb3.h"
#include "hw/ppc/pnv.h"
#include "hw/pci/msi.h"
#include "monitor/monitor.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "sysemu/reset.h"
static uint64_t phb3_msi_ive_addr(PnvPHB3 *phb, int srcno)
{
uint64_t ivtbar = phb->regs[PHB_IVT_BAR >> 3];
uint64_t phbctl = phb->regs[PHB_CONTROL >> 3];
if (!(ivtbar & PHB_IVT_BAR_ENABLE)) {
qemu_log_mask(LOG_GUEST_ERROR, "Failed access to disable IVT BAR !");
return 0;
}
if (srcno >= (ivtbar & PHB_IVT_LENGTH_MASK)) {
qemu_log_mask(LOG_GUEST_ERROR, "MSI out of bounds (%d vs 0x%"PRIx64")",
srcno, (uint64_t) (ivtbar & PHB_IVT_LENGTH_MASK));
return 0;
}
ivtbar &= PHB_IVT_BASE_ADDRESS_MASK;
if (phbctl & PHB_CTRL_IVE_128_BYTES) {
return ivtbar + 128 * srcno;
} else {
return ivtbar + 16 * srcno;
}
}
static bool phb3_msi_read_ive(PnvPHB3 *phb, int srcno, uint64_t *out_ive)
{
uint64_t ive_addr, ive;
ive_addr = phb3_msi_ive_addr(phb, srcno);
if (!ive_addr) {
return false;
}
if (dma_memory_read(&address_space_memory, ive_addr, &ive, sizeof(ive))) {
qemu_log_mask(LOG_GUEST_ERROR, "Failed to read IVE at 0x%" PRIx64,
ive_addr);
return false;
}
*out_ive = be64_to_cpu(ive);
return true;
}
static void phb3_msi_set_p(Phb3MsiState *msi, int srcno, uint8_t gen)
{
uint64_t ive_addr;
uint8_t p = 0x01 | (gen << 1);
ive_addr = phb3_msi_ive_addr(msi->phb, srcno);
if (!ive_addr) {
return;
}
if (dma_memory_write(&address_space_memory, ive_addr + 4, &p, 1)) {
qemu_log_mask(LOG_GUEST_ERROR,
"Failed to write IVE (set P) at 0x%" PRIx64, ive_addr);
}
}
static void phb3_msi_set_q(Phb3MsiState *msi, int srcno)
{
uint64_t ive_addr;
uint8_t q = 0x01;
ive_addr = phb3_msi_ive_addr(msi->phb, srcno);
if (!ive_addr) {
return;
}
if (dma_memory_write(&address_space_memory, ive_addr + 5, &q, 1)) {
qemu_log_mask(LOG_GUEST_ERROR,
"Failed to write IVE (set Q) at 0x%" PRIx64, ive_addr);
}
}
static void phb3_msi_try_send(Phb3MsiState *msi, int srcno, bool force)
{
ICSState *ics = ICS(msi);
uint64_t ive;
uint64_t server, prio, pq, gen;
if (!phb3_msi_read_ive(msi->phb, srcno, &ive)) {
return;
}
server = GETFIELD(IODA2_IVT_SERVER, ive);
prio = GETFIELD(IODA2_IVT_PRIORITY, ive);
if (!force) {
pq = GETFIELD(IODA2_IVT_Q, ive) | (GETFIELD(IODA2_IVT_P, ive) << 1);
} else {
pq = 0;
}
gen = GETFIELD(IODA2_IVT_GEN, ive);
/*
* The low order 2 bits are the link pointer (Type II interrupts).
* Shift back to get a valid IRQ server.
*/
server >>= 2;
switch (pq) {
case 0: /* 00 */
if (prio == 0xff) {
/* Masked, set Q */
phb3_msi_set_q(msi, srcno);
} else {
/* Enabled, set P and send */
phb3_msi_set_p(msi, srcno, gen);
icp_irq(ics, server, srcno + ics->offset, prio);
}
break;
case 2: /* 10 */
/* Already pending, set Q */
phb3_msi_set_q(msi, srcno);
break;
case 1: /* 01 */
case 3: /* 11 */
default:
/* Just drop stuff if Q already set */
break;
}
}
static void phb3_msi_set_irq(void *opaque, int srcno, int val)
{
Phb3MsiState *msi = PHB3_MSI(opaque);
if (val) {
phb3_msi_try_send(msi, srcno, false);
}
}
void pnv_phb3_msi_send(Phb3MsiState *msi, uint64_t addr, uint16_t data,
int32_t dev_pe)
{
ICSState *ics = ICS(msi);
uint64_t ive;
uint16_t pe;
uint32_t src = ((addr >> 4) & 0xffff) | (data & 0x1f);
if (src >= ics->nr_irqs) {
qemu_log_mask(LOG_GUEST_ERROR, "MSI %d out of bounds", src);
return;
}
if (dev_pe >= 0) {
if (!phb3_msi_read_ive(msi->phb, src, &ive)) {
return;
}
pe = GETFIELD(IODA2_IVT_PE, ive);
if (pe != dev_pe) {
qemu_log_mask(LOG_GUEST_ERROR,
"MSI %d send by PE#%d but assigned to PE#%d",
src, dev_pe, pe);
return;
}
}
qemu_irq_pulse(msi->qirqs[src]);
}
void pnv_phb3_msi_ffi(Phb3MsiState *msi, uint64_t val)
{
/* Emit interrupt */
pnv_phb3_msi_send(msi, val, 0, -1);
/* Clear FFI lock */
msi->phb->regs[PHB_FFI_LOCK >> 3] = 0;
}
static void phb3_msi_reject(ICSState *ics, uint32_t nr)
{
Phb3MsiState *msi = PHB3_MSI(ics);
unsigned int srcno = nr - ics->offset;
unsigned int idx = srcno >> 6;
unsigned int bit = 1ull << (srcno & 0x3f);
assert(srcno < PHB3_MAX_MSI);
msi->rba[idx] |= bit;
msi->rba_sum |= (1u << idx);
}
static void phb3_msi_resend(ICSState *ics)
{
Phb3MsiState *msi = PHB3_MSI(ics);
unsigned int i, j;
if (msi->rba_sum == 0) {
return;
}
for (i = 0; i < 32; i++) {
if ((msi->rba_sum & (1u << i)) == 0) {
continue;
}
msi->rba_sum &= ~(1u << i);
for (j = 0; j < 64; j++) {
if ((msi->rba[i] & (1ull << j)) == 0) {
continue;
}
msi->rba[i] &= ~(1u << j);
phb3_msi_try_send(msi, i * 64 + j, true);
}
}
}
static void phb3_msi_reset(DeviceState *dev)
{
Phb3MsiState *msi = PHB3_MSI(dev);
ICSStateClass *icsc = ICS_GET_CLASS(dev);
icsc->parent_reset(dev);
memset(msi->rba, 0, sizeof(msi->rba));
msi->rba_sum = 0;
}
static void phb3_msi_reset_handler(void *dev)
{
phb3_msi_reset(dev);
}
void pnv_phb3_msi_update_config(Phb3MsiState *msi, uint32_t base,
uint32_t count)
{
ICSState *ics = ICS(msi);
if (count > PHB3_MAX_MSI) {
count = PHB3_MAX_MSI;
}
ics->nr_irqs = count;
ics->offset = base;
}
static void phb3_msi_realize(DeviceState *dev, Error **errp)
{
Phb3MsiState *msi = PHB3_MSI(dev);
ICSState *ics = ICS(msi);
ICSStateClass *icsc = ICS_GET_CLASS(ics);
Error *local_err = NULL;
assert(msi->phb);
icsc->parent_realize(dev, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
msi->qirqs = qemu_allocate_irqs(phb3_msi_set_irq, msi, ics->nr_irqs);
qemu_register_reset(phb3_msi_reset_handler, dev);
}
static void phb3_msi_instance_init(Object *obj)
{
Phb3MsiState *msi = PHB3_MSI(obj);
ICSState *ics = ICS(obj);
object_property_add_link(obj, "phb", TYPE_PNV_PHB3,
(Object **)&msi->phb,
object_property_allow_set_link,
OBJ_PROP_LINK_STRONG,
&error_abort);
/* Will be overriden later */
ics->offset = 0;
}
static void phb3_msi_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ICSStateClass *isc = ICS_CLASS(klass);
device_class_set_parent_realize(dc, phb3_msi_realize,
&isc->parent_realize);
device_class_set_parent_reset(dc, phb3_msi_reset,
&isc->parent_reset);
isc->reject = phb3_msi_reject;
isc->resend = phb3_msi_resend;
}
static const TypeInfo phb3_msi_info = {
.name = TYPE_PHB3_MSI,
.parent = TYPE_ICS,
.instance_size = sizeof(Phb3MsiState),
.class_init = phb3_msi_class_init,
.class_size = sizeof(ICSStateClass),
.instance_init = phb3_msi_instance_init,
};
static void pnv_phb3_msi_register_types(void)
{
type_register_static(&phb3_msi_info);
}
type_init(pnv_phb3_msi_register_types);
void pnv_phb3_msi_pic_print_info(Phb3MsiState *msi, Monitor *mon)
{
ICSState *ics = ICS(msi);
int i;
monitor_printf(mon, "ICS %4x..%4x %p\n",
ics->offset, ics->offset + ics->nr_irqs - 1, ics);
for (i = 0; i < ics->nr_irqs; i++) {
uint64_t ive;
if (!phb3_msi_read_ive(msi->phb, i, &ive)) {
return;
}
if (GETFIELD(IODA2_IVT_PRIORITY, ive) == 0xff) {
continue;
}
monitor_printf(mon, " %4x %c%c server=%04x prio=%02x gen=%d\n",
ics->offset + i,
GETFIELD(IODA2_IVT_P, ive) ? 'P' : '-',
GETFIELD(IODA2_IVT_Q, ive) ? 'Q' : '-',
(uint32_t) GETFIELD(IODA2_IVT_SERVER, ive) >> 2,
(uint32_t) GETFIELD(IODA2_IVT_PRIORITY, ive),
(uint32_t) GETFIELD(IODA2_IVT_GEN, ive));
}
}

357
hw/pci-host/pnv_phb3_pbcq.c Normal file
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@ -0,0 +1,357 @@
/*
* QEMU PowerPC PowerNV (POWER8) PHB3 model
*
* Copyright (c) 2014-2020, IBM Corporation.
*
* This code is licensed under the GPL version 2 or later. See the
* COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "qemu/log.h"
#include "target/ppc/cpu.h"
#include "hw/ppc/fdt.h"
#include "hw/pci-host/pnv_phb3_regs.h"
#include "hw/pci-host/pnv_phb3.h"
#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_xscom.h"
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pci_bus.h"
#include <libfdt.h>
#define phb3_pbcq_error(pbcq, fmt, ...) \
qemu_log_mask(LOG_GUEST_ERROR, "phb3_pbcq[%d:%d]: " fmt "\n", \
(pbcq)->phb->chip_id, (pbcq)->phb->phb_id, ## __VA_ARGS__)
static uint64_t pnv_pbcq_nest_xscom_read(void *opaque, hwaddr addr,
unsigned size)
{
PnvPBCQState *pbcq = PNV_PBCQ(opaque);
uint32_t offset = addr >> 3;
return pbcq->nest_regs[offset];
}
static uint64_t pnv_pbcq_pci_xscom_read(void *opaque, hwaddr addr,
unsigned size)
{
PnvPBCQState *pbcq = PNV_PBCQ(opaque);
uint32_t offset = addr >> 3;
return pbcq->pci_regs[offset];
}
static uint64_t pnv_pbcq_spci_xscom_read(void *opaque, hwaddr addr,
unsigned size)
{
PnvPBCQState *pbcq = PNV_PBCQ(opaque);
uint32_t offset = addr >> 3;
if (offset == PBCQ_SPCI_ASB_DATA) {
return pnv_phb3_reg_read(pbcq->phb,
pbcq->spci_regs[PBCQ_SPCI_ASB_ADDR], 8);
}
return pbcq->spci_regs[offset];
}
static void pnv_pbcq_update_map(PnvPBCQState *pbcq)
{
uint64_t bar_en = pbcq->nest_regs[PBCQ_NEST_BAR_EN];
uint64_t bar, mask, size;
/*
* NOTE: This will really not work well if those are remapped
* after the PHB has created its sub regions. We could do better
* if we had a way to resize regions but we don't really care
* that much in practice as the stuff below really only happens
* once early during boot
*/
/* Handle unmaps */
if (memory_region_is_mapped(&pbcq->mmbar0) &&
!(bar_en & PBCQ_NEST_BAR_EN_MMIO0)) {
memory_region_del_subregion(get_system_memory(), &pbcq->mmbar0);
}
if (memory_region_is_mapped(&pbcq->mmbar1) &&
!(bar_en & PBCQ_NEST_BAR_EN_MMIO1)) {
memory_region_del_subregion(get_system_memory(), &pbcq->mmbar1);
}
if (memory_region_is_mapped(&pbcq->phbbar) &&
!(bar_en & PBCQ_NEST_BAR_EN_PHB)) {
memory_region_del_subregion(get_system_memory(), &pbcq->phbbar);
}
/* Update PHB */
pnv_phb3_update_regions(pbcq->phb);
/* Handle maps */
if (!memory_region_is_mapped(&pbcq->mmbar0) &&
(bar_en & PBCQ_NEST_BAR_EN_MMIO0)) {
bar = pbcq->nest_regs[PBCQ_NEST_MMIO_BAR0] >> 14;
mask = pbcq->nest_regs[PBCQ_NEST_MMIO_MASK0];
size = ((~mask) >> 14) + 1;
memory_region_init(&pbcq->mmbar0, OBJECT(pbcq), "pbcq-mmio0", size);
memory_region_add_subregion(get_system_memory(), bar, &pbcq->mmbar0);
pbcq->mmio0_base = bar;
pbcq->mmio0_size = size;
}
if (!memory_region_is_mapped(&pbcq->mmbar1) &&
(bar_en & PBCQ_NEST_BAR_EN_MMIO1)) {
bar = pbcq->nest_regs[PBCQ_NEST_MMIO_BAR1] >> 14;
mask = pbcq->nest_regs[PBCQ_NEST_MMIO_MASK1];
size = ((~mask) >> 14) + 1;
memory_region_init(&pbcq->mmbar1, OBJECT(pbcq), "pbcq-mmio1", size);
memory_region_add_subregion(get_system_memory(), bar, &pbcq->mmbar1);
pbcq->mmio1_base = bar;
pbcq->mmio1_size = size;
}
if (!memory_region_is_mapped(&pbcq->phbbar)
&& (bar_en & PBCQ_NEST_BAR_EN_PHB)) {
bar = pbcq->nest_regs[PBCQ_NEST_PHB_BAR] >> 14;
size = 0x1000;
memory_region_init(&pbcq->phbbar, OBJECT(pbcq), "pbcq-phb", size);
memory_region_add_subregion(get_system_memory(), bar, &pbcq->phbbar);
}
/* Update PHB */
pnv_phb3_update_regions(pbcq->phb);
}
static void pnv_pbcq_nest_xscom_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PnvPBCQState *pbcq = PNV_PBCQ(opaque);
uint32_t reg = addr >> 3;
switch (reg) {
case PBCQ_NEST_MMIO_BAR0:
case PBCQ_NEST_MMIO_BAR1:
case PBCQ_NEST_MMIO_MASK0:
case PBCQ_NEST_MMIO_MASK1:
if (pbcq->nest_regs[PBCQ_NEST_BAR_EN] &
(PBCQ_NEST_BAR_EN_MMIO0 |
PBCQ_NEST_BAR_EN_MMIO1)) {
phb3_pbcq_error(pbcq, "Changing enabled BAR unsupported");
}
pbcq->nest_regs[reg] = val & 0xffffffffc0000000ull;
break;
case PBCQ_NEST_PHB_BAR:
if (pbcq->nest_regs[PBCQ_NEST_BAR_EN] & PBCQ_NEST_BAR_EN_PHB) {
phb3_pbcq_error(pbcq, "Changing enabled BAR unsupported");
}
pbcq->nest_regs[reg] = val & 0xfffffffffc000000ull;
break;
case PBCQ_NEST_BAR_EN:
pbcq->nest_regs[reg] = val & 0xf800000000000000ull;
pnv_pbcq_update_map(pbcq);
pnv_phb3_remap_irqs(pbcq->phb);
break;
case PBCQ_NEST_IRSN_COMPARE:
case PBCQ_NEST_IRSN_MASK:
pbcq->nest_regs[reg] = val & PBCQ_NEST_IRSN_COMP;
pnv_phb3_remap_irqs(pbcq->phb);
break;
case PBCQ_NEST_LSI_SRC_ID:
pbcq->nest_regs[reg] = val & PBCQ_NEST_LSI_SRC;
pnv_phb3_remap_irqs(pbcq->phb);
break;
default:
phb3_pbcq_error(pbcq, "%s @0x%"HWADDR_PRIx"=%"PRIx64, __func__,
addr, val);
}
}
static void pnv_pbcq_pci_xscom_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PnvPBCQState *pbcq = PNV_PBCQ(opaque);
uint32_t reg = addr >> 3;
switch (reg) {
case PBCQ_PCI_BAR2:
pbcq->pci_regs[reg] = val & 0xfffffffffc000000ull;
pnv_pbcq_update_map(pbcq);
default:
phb3_pbcq_error(pbcq, "%s @0x%"HWADDR_PRIx"=%"PRIx64, __func__,
addr, val);
}
}
static void pnv_pbcq_spci_xscom_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PnvPBCQState *pbcq = PNV_PBCQ(opaque);
uint32_t reg = addr >> 3;
switch (reg) {
case PBCQ_SPCI_ASB_ADDR:
pbcq->spci_regs[reg] = val & 0xfff;
break;
case PBCQ_SPCI_ASB_STATUS:
pbcq->spci_regs[reg] &= ~val;
break;
case PBCQ_SPCI_ASB_DATA:
pnv_phb3_reg_write(pbcq->phb, pbcq->spci_regs[PBCQ_SPCI_ASB_ADDR],
val, 8);
break;
case PBCQ_SPCI_AIB_CAPP_EN:
case PBCQ_SPCI_CAPP_SEC_TMR:
break;
default:
phb3_pbcq_error(pbcq, "%s @0x%"HWADDR_PRIx"=%"PRIx64, __func__,
addr, val);
}
}
static const MemoryRegionOps pnv_pbcq_nest_xscom_ops = {
.read = pnv_pbcq_nest_xscom_read,
.write = pnv_pbcq_nest_xscom_write,
.valid.min_access_size = 8,
.valid.max_access_size = 8,
.impl.min_access_size = 8,
.impl.max_access_size = 8,
.endianness = DEVICE_BIG_ENDIAN,
};
static const MemoryRegionOps pnv_pbcq_pci_xscom_ops = {
.read = pnv_pbcq_pci_xscom_read,
.write = pnv_pbcq_pci_xscom_write,
.valid.min_access_size = 8,
.valid.max_access_size = 8,
.impl.min_access_size = 8,
.impl.max_access_size = 8,
.endianness = DEVICE_BIG_ENDIAN,
};
static const MemoryRegionOps pnv_pbcq_spci_xscom_ops = {
.read = pnv_pbcq_spci_xscom_read,
.write = pnv_pbcq_spci_xscom_write,
.valid.min_access_size = 8,
.valid.max_access_size = 8,
.impl.min_access_size = 8,
.impl.max_access_size = 8,
.endianness = DEVICE_BIG_ENDIAN,
};
static void pnv_pbcq_default_bars(PnvPBCQState *pbcq)
{
uint64_t mm0, mm1, reg;
PnvPHB3 *phb = pbcq->phb;
mm0 = 0x3d00000000000ull + 0x4000000000ull * phb->chip_id +
0x1000000000ull * phb->phb_id;
mm1 = 0x3ff8000000000ull + 0x0200000000ull * phb->chip_id +
0x0080000000ull * phb->phb_id;
reg = 0x3fffe40000000ull + 0x0000400000ull * phb->chip_id +
0x0000100000ull * phb->phb_id;
pbcq->nest_regs[PBCQ_NEST_MMIO_BAR0] = mm0 << 14;
pbcq->nest_regs[PBCQ_NEST_MMIO_BAR1] = mm1 << 14;
pbcq->nest_regs[PBCQ_NEST_PHB_BAR] = reg << 14;
pbcq->nest_regs[PBCQ_NEST_MMIO_MASK0] = 0x3fff000000000ull << 14;
pbcq->nest_regs[PBCQ_NEST_MMIO_MASK1] = 0x3ffff80000000ull << 14;
pbcq->pci_regs[PBCQ_PCI_BAR2] = reg << 14;
}
static void pnv_pbcq_realize(DeviceState *dev, Error **errp)
{
PnvPBCQState *pbcq = PNV_PBCQ(dev);
PnvPHB3 *phb;
char name[32];
assert(pbcq->phb);
phb = pbcq->phb;
/* TODO: Fix OPAL to do that: establish default BAR values */
pnv_pbcq_default_bars(pbcq);
/* Initialize the XSCOM region for the PBCQ registers */
snprintf(name, sizeof(name), "xscom-pbcq-nest-%d.%d",
phb->chip_id, phb->phb_id);
pnv_xscom_region_init(&pbcq->xscom_nest_regs, OBJECT(dev),
&pnv_pbcq_nest_xscom_ops, pbcq, name,
PNV_XSCOM_PBCQ_NEST_SIZE);
snprintf(name, sizeof(name), "xscom-pbcq-pci-%d.%d",
phb->chip_id, phb->phb_id);
pnv_xscom_region_init(&pbcq->xscom_pci_regs, OBJECT(dev),
&pnv_pbcq_pci_xscom_ops, pbcq, name,
PNV_XSCOM_PBCQ_PCI_SIZE);
snprintf(name, sizeof(name), "xscom-pbcq-spci-%d.%d",
phb->chip_id, phb->phb_id);
pnv_xscom_region_init(&pbcq->xscom_spci_regs, OBJECT(dev),
&pnv_pbcq_spci_xscom_ops, pbcq, name,
PNV_XSCOM_PBCQ_SPCI_SIZE);
}
static int pnv_pbcq_dt_xscom(PnvXScomInterface *dev, void *fdt,
int xscom_offset)
{
const char compat[] = "ibm,power8-pbcq";
PnvPHB3 *phb = PNV_PBCQ(dev)->phb;
char *name;
int offset;
uint32_t lpc_pcba = PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id;
uint32_t reg[] = {
cpu_to_be32(lpc_pcba),
cpu_to_be32(PNV_XSCOM_PBCQ_NEST_SIZE),
cpu_to_be32(PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id),
cpu_to_be32(PNV_XSCOM_PBCQ_PCI_SIZE),
cpu_to_be32(PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id),
cpu_to_be32(PNV_XSCOM_PBCQ_SPCI_SIZE)
};
name = g_strdup_printf("pbcq@%x", lpc_pcba);
offset = fdt_add_subnode(fdt, xscom_offset, name);
_FDT(offset);
g_free(name);
_FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
_FDT((fdt_setprop_cell(fdt, offset, "ibm,phb-index", phb->phb_id)));
_FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", phb->chip_id)));
_FDT((fdt_setprop(fdt, offset, "compatible", compat,
sizeof(compat))));
return 0;
}
static void phb3_pbcq_instance_init(Object *obj)
{
PnvPBCQState *pbcq = PNV_PBCQ(obj);
object_property_add_link(obj, "phb", TYPE_PNV_PHB3,
(Object **)&pbcq->phb,
object_property_allow_set_link,
OBJ_PROP_LINK_STRONG,
&error_abort);
}
static void pnv_pbcq_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
xdc->dt_xscom = pnv_pbcq_dt_xscom;
dc->realize = pnv_pbcq_realize;
}
static const TypeInfo pnv_pbcq_type_info = {
.name = TYPE_PNV_PBCQ,
.parent = TYPE_DEVICE,
.instance_size = sizeof(PnvPBCQState),
.instance_init = phb3_pbcq_instance_init,
.class_init = pnv_pbcq_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_PNV_XSCOM_INTERFACE },
{ }
}
};
static void pnv_pbcq_register_types(void)
{
type_register_static(&pnv_pbcq_type_info);
}
type_init(pnv_pbcq_register_types)

69
hw/ppc/pnv.c
View File

@ -616,8 +616,13 @@ static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
{
Pnv8Chip *chip8 = PNV8_CHIP(chip);
int i;
ics_pic_print_info(&chip8->psi.ics, mon);
for (i = 0; i < chip->num_phbs; i++) {
pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon);
ics_pic_print_info(&chip8->phbs[i].lsis, mon);
}
}
static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
@ -1026,7 +1031,10 @@ static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
static void pnv_chip_power8_instance_init(Object *obj)
{
PnvChip *chip = PNV_CHIP(obj);
Pnv8Chip *chip8 = PNV8_CHIP(obj);
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
int i;
object_property_add_link(obj, "xics", TYPE_XICS_FABRIC,
(Object **)&chip8->xics,
@ -1045,6 +1053,17 @@ static void pnv_chip_power8_instance_init(Object *obj)
object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer),
TYPE_PNV8_HOMER, &error_abort, NULL);
for (i = 0; i < pcc->num_phbs; i++) {
object_initialize_child(obj, "phb[*]", &chip8->phbs[i],
sizeof(chip8->phbs[i]), TYPE_PNV_PHB3,
&error_abort, NULL);
}
/*
* Number of PHBs is the chip default
*/
chip->num_phbs = pcc->num_phbs;
}
static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
@ -1083,6 +1102,7 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
Pnv8Chip *chip8 = PNV8_CHIP(dev);
Pnv8Psi *psi8 = &chip8->psi;
Error *local_err = NULL;
int i;
assert(chip8->xics);
@ -1163,6 +1183,33 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
/* Homer mmio region */
memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
&chip8->homer.regs);
/* PHB3 controllers */
for (i = 0; i < chip->num_phbs; i++) {
PnvPHB3 *phb = &chip8->phbs[i];
PnvPBCQState *pbcq = &phb->pbcq;
object_property_set_int(OBJECT(phb), i, "index", &error_fatal);
object_property_set_int(OBJECT(phb), chip->chip_id, "chip-id",
&error_fatal);
object_property_set_bool(OBJECT(phb), true, "realized", &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
qdev_set_parent_bus(DEVICE(phb), sysbus_get_default());
/* Populate the XSCOM address space. */
pnv_xscom_add_subregion(chip,
PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id,
&pbcq->xscom_nest_regs);
pnv_xscom_add_subregion(chip,
PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id,
&pbcq->xscom_pci_regs);
pnv_xscom_add_subregion(chip,
PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id,
&pbcq->xscom_spci_regs);
}
}
static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
@ -1178,6 +1225,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
k->cores_mask = POWER8E_CORE_MASK;
k->num_phbs = 3;
k->core_pir = pnv_chip_core_pir_p8;
k->intc_create = pnv_chip_power8_intc_create;
k->intc_reset = pnv_chip_power8_intc_reset;
@ -1201,6 +1249,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
k->cores_mask = POWER8_CORE_MASK;
k->num_phbs = 3;
k->core_pir = pnv_chip_core_pir_p8;
k->intc_create = pnv_chip_power8_intc_create;
k->intc_reset = pnv_chip_power8_intc_reset;
@ -1224,6 +1273,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
k->cores_mask = POWER8_CORE_MASK;
k->num_phbs = 3;
k->core_pir = pnv_chip_core_pir_p8;
k->intc_create = pnv_chip_power8_intc_create;
k->intc_reset = pnv_chip_power8_intc_reset;
@ -1748,14 +1798,23 @@ PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
{
PnvMachineState *pnv = PNV_MACHINE(xi);
int i;
int i, j;
for (i = 0; i < pnv->num_chips; i++) {
PnvChip *chip = pnv->chips[i];
Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
if (ics_valid_irq(&chip8->psi.ics, irq)) {
return &chip8->psi.ics;
}
for (j = 0; j < chip->num_phbs; j++) {
if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) {
return &chip8->phbs[j].lsis;
}
if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) {
return ICS(&chip8->phbs[j].msis);
}
}
}
return NULL;
}
@ -1763,11 +1822,17 @@ static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
static void pnv_ics_resend(XICSFabric *xi)
{
PnvMachineState *pnv = PNV_MACHINE(xi);
int i;
int i, j;
for (i = 0; i < pnv->num_chips; i++) {
PnvChip *chip = pnv->chips[i];
Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
ics_resend(&chip8->psi.ics);
for (j = 0; j < chip->num_phbs; j++) {
ics_resend(&chip8->phbs[j].lsis);
ics_resend(ICS(&chip8->phbs[j].msis));
}
}
}

164
include/hw/pci-host/pnv_phb3.h Normal file
View File

@ -0,0 +1,164 @@
/*
* QEMU PowerPC PowerNV (POWER8) PHB3 model
*
* Copyright (c) 2014-2020, IBM Corporation.
*
* This code is licensed under the GPL version 2 or later. See the
* COPYING file in the top-level directory.
*/
#ifndef PCI_HOST_PNV_PHB3_H
#define PCI_HOST_PNV_PHB3_H
#include "hw/pci/pcie_host.h"
#include "hw/pci/pcie_port.h"
#include "hw/ppc/xics.h"
typedef struct PnvPHB3 PnvPHB3;
/*
* PHB3 XICS Source for MSIs
*/
#define TYPE_PHB3_MSI "phb3-msi"
#define PHB3_MSI(obj) OBJECT_CHECK(Phb3MsiState, (obj), TYPE_PHB3_MSI)
#define PHB3_MAX_MSI 2048
typedef struct Phb3MsiState {
ICSState ics;
qemu_irq *qirqs;
PnvPHB3 *phb;
uint64_t rba[PHB3_MAX_MSI / 64];
uint32_t rba_sum;
} Phb3MsiState;
void pnv_phb3_msi_update_config(Phb3MsiState *msis, uint32_t base,
uint32_t count);
void pnv_phb3_msi_send(Phb3MsiState *msis, uint64_t addr, uint16_t data,
int32_t dev_pe);
void pnv_phb3_msi_ffi(Phb3MsiState *msis, uint64_t val);
void pnv_phb3_msi_pic_print_info(Phb3MsiState *msis, Monitor *mon);
/*
* We have one such address space wrapper per possible device under
* the PHB since they need to be assigned statically at qemu device
* creation time. The relationship to a PE is done later dynamically.
* This means we can potentially create a lot of these guys. Q35
* stores them as some kind of radix tree but we never really need to
* do fast lookups so instead we simply keep a QLIST of them for now,
* we can add the radix if needed later on.
*
* We do cache the PE number to speed things up a bit though.
*/
typedef struct PnvPhb3DMASpace {
PCIBus *bus;
uint8_t devfn;
int pe_num; /* Cached PE number */
#define PHB_INVALID_PE (-1)
PnvPHB3 *phb;
AddressSpace dma_as;
IOMMUMemoryRegion dma_mr;
MemoryRegion msi32_mr;
MemoryRegion msi64_mr;
QLIST_ENTRY(PnvPhb3DMASpace) list;
} PnvPhb3DMASpace;
/*
* PHB3 Power Bus Common Queue
*/
#define TYPE_PNV_PBCQ "pnv-pbcq"
#define PNV_PBCQ(obj) OBJECT_CHECK(PnvPBCQState, (obj), TYPE_PNV_PBCQ)
typedef struct PnvPBCQState {
DeviceState parent;
uint32_t nest_xbase;
uint32_t spci_xbase;
uint32_t pci_xbase;
#define PBCQ_NEST_REGS_COUNT 0x46
#define PBCQ_PCI_REGS_COUNT 0x15
#define PBCQ_SPCI_REGS_COUNT 0x5
uint64_t nest_regs[PBCQ_NEST_REGS_COUNT];
uint64_t spci_regs[PBCQ_SPCI_REGS_COUNT];
uint64_t pci_regs[PBCQ_PCI_REGS_COUNT];
MemoryRegion mmbar0;
MemoryRegion mmbar1;
MemoryRegion phbbar;
uint64_t mmio0_base;
uint64_t mmio0_size;
uint64_t mmio1_base;
uint64_t mmio1_size;
PnvPHB3 *phb;
MemoryRegion xscom_nest_regs;
MemoryRegion xscom_pci_regs;
MemoryRegion xscom_spci_regs;
} PnvPBCQState;
/*
* PHB3 PCIe Root port
*/
#define TYPE_PNV_PHB3_ROOT_BUS "pnv-phb3-root-bus"
#define TYPE_PNV_PHB3_ROOT_PORT "pnv-phb3-root-port"
typedef struct PnvPHB3RootPort {
PCIESlot parent_obj;
} PnvPHB3RootPort;
/*
* PHB3 PCIe Host Bridge for PowerNV machines (POWER8)
*/
#define TYPE_PNV_PHB3 "pnv-phb3"
#define PNV_PHB3(obj) OBJECT_CHECK(PnvPHB3, (obj), TYPE_PNV_PHB3)
#define PNV_PHB3_NUM_M64 16
#define PNV_PHB3_NUM_REGS (0x1000 >> 3)
#define PNV_PHB3_NUM_LSI 8
#define PNV_PHB3_NUM_PE 256
#define PCI_MMIO_TOTAL_SIZE (0x1ull << 60)
struct PnvPHB3 {
PCIExpressHost parent_obj;
uint32_t chip_id;
uint32_t phb_id;
char bus_path[8];
uint64_t regs[PNV_PHB3_NUM_REGS];
MemoryRegion mr_regs;
MemoryRegion mr_m32;
MemoryRegion mr_m64[PNV_PHB3_NUM_M64];
MemoryRegion pci_mmio;
MemoryRegion pci_io;
uint64_t ioda_LIST[8];
uint64_t ioda_LXIVT[8];
uint64_t ioda_TVT[512];
uint64_t ioda_M64BT[16];
uint64_t ioda_MDT[256];
uint64_t ioda_PEEV[4];
uint32_t total_irq;
ICSState lsis;
qemu_irq *qirqs;
Phb3MsiState msis;
PnvPBCQState pbcq;
PnvPHB3RootPort root;
QLIST_HEAD(, PnvPhb3DMASpace) dma_spaces;
};
uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size);
void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size);
void pnv_phb3_update_regions(PnvPHB3 *phb);
void pnv_phb3_remap_irqs(PnvPHB3 *phb);
#endif /* PCI_HOST_PNV_PHB3_H */

450
include/hw/pci-host/pnv_phb3_regs.h Normal file
View File

@ -0,0 +1,450 @@
/*
* QEMU PowerPC PowerNV (POWER8) PHB3 model
*
* Copyright (c) 2013-2020, IBM Corporation.
*
* This code is licensed under the GPL version 2 or later. See the
* COPYING file in the top-level directory.
*/
#ifndef PCI_HOST_PNV_PHB3_REGS_H
#define PCI_HOST_PNV_PHB3_REGS_H
#include "qemu/host-utils.h"
/*
* QEMU version of the GETFIELD/SETFIELD macros
*
* These are common with the PnvXive model.
*/
static inline uint64_t GETFIELD(uint64_t mask, uint64_t word)
{
return (word & mask) >> ctz64(mask);
}
static inline uint64_t SETFIELD(uint64_t mask, uint64_t word,
uint64_t value)
{
return (word & ~mask) | ((value << ctz64(mask)) & mask);
}
/*
* PBCQ XSCOM registers
*/
#define PBCQ_NEST_IRSN_COMPARE 0x1a
#define PBCQ_NEST_IRSN_COMP PPC_BITMASK(0, 18)
#define PBCQ_NEST_IRSN_MASK 0x1b
#define PBCQ_NEST_LSI_SRC_ID 0x1f
#define PBCQ_NEST_LSI_SRC PPC_BITMASK(0, 7)
#define PBCQ_NEST_REGS_COUNT 0x46
#define PBCQ_NEST_MMIO_BAR0 0x40
#define PBCQ_NEST_MMIO_BAR1 0x41
#define PBCQ_NEST_PHB_BAR 0x42
#define PBCQ_NEST_MMIO_MASK0 0x43
#define PBCQ_NEST_MMIO_MASK1 0x44
#define PBCQ_NEST_BAR_EN 0x45
#define PBCQ_NEST_BAR_EN_MMIO0 PPC_BIT(0)
#define PBCQ_NEST_BAR_EN_MMIO1 PPC_BIT(1)
#define PBCQ_NEST_BAR_EN_PHB PPC_BIT(2)
#define PBCQ_NEST_BAR_EN_IRSN_RX PPC_BIT(3)
#define PBCQ_NEST_BAR_EN_IRSN_TX PPC_BIT(4)
#define PBCQ_PCI_REGS_COUNT 0x15
#define PBCQ_PCI_BAR2 0x0b
#define PBCQ_SPCI_REGS_COUNT 0x5
#define PBCQ_SPCI_ASB_ADDR 0x0
#define PBCQ_SPCI_ASB_STATUS 0x1
#define PBCQ_SPCI_ASB_DATA 0x2
#define PBCQ_SPCI_AIB_CAPP_EN 0x3
#define PBCQ_SPCI_CAPP_SEC_TMR 0x4
/*
* PHB MMIO registers
*/
/* PHB Fundamental register set A */
#define PHB_LSI_SOURCE_ID 0x100
#define PHB_LSI_SRC_ID PPC_BITMASK(5, 12)
#define PHB_DMA_CHAN_STATUS 0x110
#define PHB_DMA_CHAN_ANY_ERR PPC_BIT(27)
#define PHB_DMA_CHAN_ANY_ERR1 PPC_BIT(28)
#define PHB_DMA_CHAN_ANY_FREEZE PPC_BIT(29)
#define PHB_CPU_LOADSTORE_STATUS 0x120
#define PHB_CPU_LS_ANY_ERR PPC_BIT(27)
#define PHB_CPU_LS_ANY_ERR1 PPC_BIT(28)
#define PHB_CPU_LS_ANY_FREEZE PPC_BIT(29)
#define PHB_DMA_MSI_NODE_ID 0x128
#define PHB_DMAMSI_NID_FIXED PPC_BIT(0)
#define PHB_DMAMSI_NID PPC_BITMASK(24, 31)
#define PHB_CONFIG_DATA 0x130
#define PHB_LOCK0 0x138
#define PHB_CONFIG_ADDRESS 0x140
#define PHB_CA_ENABLE PPC_BIT(0)
#define PHB_CA_BUS PPC_BITMASK(4, 11)
#define PHB_CA_DEV PPC_BITMASK(12, 16)
#define PHB_CA_FUNC PPC_BITMASK(17, 19)
#define PHB_CA_REG PPC_BITMASK(20, 31)
#define PHB_CA_PE PPC_BITMASK(40, 47)
#define PHB_LOCK1 0x148
#define PHB_IVT_BAR 0x150
#define PHB_IVT_BAR_ENABLE PPC_BIT(0)
#define PHB_IVT_BASE_ADDRESS_MASK PPC_BITMASK(14, 48)
#define PHB_IVT_LENGTH_MASK PPC_BITMASK(52, 63)
#define PHB_RBA_BAR 0x158
#define PHB_RBA_BAR_ENABLE PPC_BIT(0)
#define PHB_RBA_BASE_ADDRESS PPC_BITMASK(14, 55)
#define PHB_PHB3_CONFIG 0x160
#define PHB_PHB3C_64B_TCE_EN PPC_BIT(2)
#define PHB_PHB3C_32BIT_MSI_EN PPC_BIT(8)
#define PHB_PHB3C_64BIT_MSI_EN PPC_BIT(14)
#define PHB_PHB3C_M32_EN PPC_BIT(16)
#define PHB_RTT_BAR 0x168
#define PHB_RTT_BAR_ENABLE PPC_BIT(0)
#define PHB_RTT_BASE_ADDRESS_MASK PPC_BITMASK(14, 46)
#define PHB_PELTV_BAR 0x188
#define PHB_PELTV_BAR_ENABLE PPC_BIT(0)
#define PHB_PELTV_BASE_ADDRESS PPC_BITMASK(14, 50)
#define PHB_M32_BASE_ADDR 0x190
#define PHB_M32_BASE_MASK 0x198
#define PHB_M32_START_ADDR 0x1a0
#define PHB_PEST_BAR 0x1a8
#define PHB_PEST_BAR_ENABLE PPC_BIT(0)
#define PHB_PEST_BASE_ADDRESS PPC_BITMASK(14, 51)
#define PHB_M64_UPPER_BITS 0x1f0
#define PHB_INTREP_TIMER 0x1f8
#define PHB_DMARD_SYNC 0x200
#define PHB_DMARD_SYNC_START PPC_BIT(0)
#define PHB_DMARD_SYNC_COMPLETE PPC_BIT(1)
#define PHB_RTC_INVALIDATE 0x208
#define PHB_RTC_INVALIDATE_ALL PPC_BIT(0)
#define PHB_RTC_INVALIDATE_RID PPC_BITMASK(16, 31)
#define PHB_TCE_KILL 0x210
#define PHB_TCE_KILL_ALL PPC_BIT(0)
#define PHB_TCE_SPEC_CTL 0x218
#define PHB_IODA_ADDR 0x220
#define PHB_IODA_AD_AUTOINC PPC_BIT(0)
#define PHB_IODA_AD_TSEL PPC_BITMASK(11, 15)
#define PHB_IODA_AD_TADR PPC_BITMASK(55, 63)
#define PHB_IODA_DATA0 0x228
#define PHB_FFI_REQUEST 0x238
#define PHB_FFI_LOCK_CLEAR PPC_BIT(3)
#define PHB_FFI_REQUEST_ISN PPC_BITMASK(49, 59)
#define PHB_FFI_LOCK 0x240
#define PHB_FFI_LOCK_STATE PPC_BIT(0)
#define PHB_XIVE_UPDATE 0x248 /* Broken in DD1 */
#define PHB_PHB3_GEN_CAP 0x250
#define PHB_PHB3_TCE_CAP 0x258
#define PHB_PHB3_IRQ_CAP 0x260
#define PHB_PHB3_EEH_CAP 0x268
#define PHB_IVC_INVALIDATE 0x2a0
#define PHB_IVC_INVALIDATE_ALL PPC_BIT(0)
#define PHB_IVC_INVALIDATE_SID PPC_BITMASK(16, 31)
#define PHB_IVC_UPDATE 0x2a8
#define PHB_IVC_UPDATE_ENABLE_P PPC_BIT(0)
#define PHB_IVC_UPDATE_ENABLE_Q PPC_BIT(1)
#define PHB_IVC_UPDATE_ENABLE_SERVER PPC_BIT(2)
#define PHB_IVC_UPDATE_ENABLE_PRI PPC_BIT(3)
#define PHB_IVC_UPDATE_ENABLE_GEN PPC_BIT(4)
#define PHB_IVC_UPDATE_ENABLE_CON PPC_BIT(5)
#define PHB_IVC_UPDATE_GEN_MATCH PPC_BITMASK(6, 7)
#define PHB_IVC_UPDATE_SERVER PPC_BITMASK(8, 23)
#define PHB_IVC_UPDATE_PRI PPC_BITMASK(24, 31)
#define PHB_IVC_UPDATE_GEN PPC_BITMASK(32, 33)
#define PHB_IVC_UPDATE_P PPC_BITMASK(34, 34)
#define PHB_IVC_UPDATE_Q PPC_BITMASK(35, 35)
#define PHB_IVC_UPDATE_SID PPC_BITMASK(48, 63)
#define PHB_PAPR_ERR_INJ_CTL 0x2b0
#define PHB_PAPR_ERR_INJ_CTL_INB PPC_BIT(0)
#define PHB_PAPR_ERR_INJ_CTL_OUTB PPC_BIT(1)
#define PHB_PAPR_ERR_INJ_CTL_STICKY PPC_BIT(2)
#define PHB_PAPR_ERR_INJ_CTL_CFG PPC_BIT(3)
#define PHB_PAPR_ERR_INJ_CTL_RD PPC_BIT(4)
#define PHB_PAPR_ERR_INJ_CTL_WR PPC_BIT(5)
#define PHB_PAPR_ERR_INJ_CTL_FREEZE PPC_BIT(6)
#define PHB_PAPR_ERR_INJ_ADDR 0x2b8
#define PHB_PAPR_ERR_INJ_ADDR_MMIO PPC_BITMASK(16, 63)
#define PHB_PAPR_ERR_INJ_MASK 0x2c0
#define PHB_PAPR_ERR_INJ_MASK_CFG PPC_BITMASK(4, 11)
#define PHB_PAPR_ERR_INJ_MASK_MMIO PPC_BITMASK(16, 63)
#define PHB_ETU_ERR_SUMMARY 0x2c8
/* UTL registers */
#define UTL_SYS_BUS_CONTROL 0x400
#define UTL_STATUS 0x408
#define UTL_SYS_BUS_AGENT_STATUS 0x410
#define UTL_SYS_BUS_AGENT_ERR_SEVERITY 0x418
#define UTL_SYS_BUS_AGENT_IRQ_EN 0x420
#define UTL_SYS_BUS_BURST_SZ_CONF 0x440
#define UTL_REVISION_ID 0x448
#define UTL_BCLK_DOMAIN_DBG1 0x460
#define UTL_BCLK_DOMAIN_DBG2 0x468
#define UTL_BCLK_DOMAIN_DBG3 0x470
#define UTL_BCLK_DOMAIN_DBG4 0x478
#define UTL_BCLK_DOMAIN_DBG5 0x480
#define UTL_BCLK_DOMAIN_DBG6 0x488
#define UTL_OUT_POST_HDR_BUF_ALLOC 0x4c0
#define UTL_OUT_POST_DAT_BUF_ALLOC 0x4d0
#define UTL_IN_POST_HDR_BUF_ALLOC 0x4e0
#define UTL_IN_POST_DAT_BUF_ALLOC 0x4f0
#define UTL_OUT_NP_BUF_ALLOC 0x500
#define UTL_IN_NP_BUF_ALLOC 0x510
#define UTL_PCIE_TAGS_ALLOC 0x520
#define UTL_GBIF_READ_TAGS_ALLOC 0x530
#define UTL_PCIE_PORT_CONTROL 0x540
#define UTL_PCIE_PORT_STATUS 0x548
#define UTL_PCIE_PORT_ERROR_SEV 0x550
#define UTL_PCIE_PORT_IRQ_EN 0x558
#define UTL_RC_STATUS 0x560
#define UTL_RC_ERR_SEVERITY 0x568
#define UTL_RC_IRQ_EN 0x570
#define UTL_EP_STATUS 0x578
#define UTL_EP_ERR_SEVERITY 0x580
#define UTL_EP_ERR_IRQ_EN 0x588
#define UTL_PCI_PM_CTRL1 0x590
#define UTL_PCI_PM_CTRL2 0x598
#define UTL_GP_CTL1 0x5a0
#define UTL_GP_CTL2 0x5a8
#define UTL_PCLK_DOMAIN_DBG1 0x5b0
#define UTL_PCLK_DOMAIN_DBG2 0x5b8
#define UTL_PCLK_DOMAIN_DBG3 0x5c0
#define UTL_PCLK_DOMAIN_DBG4 0x5c8
/* PCI-E Stack registers */
#define PHB_PCIE_SYSTEM_CONFIG 0x600
#define PHB_PCIE_BUS_NUMBER 0x608
#define PHB_PCIE_SYSTEM_TEST 0x618
#define PHB_PCIE_LINK_MANAGEMENT 0x630
#define PHB_PCIE_LM_LINK_ACTIVE PPC_BIT(8)
#define PHB_PCIE_DLP_TRAIN_CTL 0x640
#define PHB_PCIE_DLP_TCTX_DISABLE PPC_BIT(1)
#define PHB_PCIE_DLP_TCRX_DISABLED PPC_BIT(16)
#define PHB_PCIE_DLP_INBAND_PRESENCE PPC_BIT(19)
#define PHB_PCIE_DLP_TC_DL_LINKUP PPC_BIT(21)
#define PHB_PCIE_DLP_TC_DL_PGRESET PPC_BIT(22)
#define PHB_PCIE_DLP_TC_DL_LINKACT PPC_BIT(23)
#define PHB_PCIE_SLOP_LOOPBACK_STATUS 0x648
#define PHB_PCIE_SYS_LINK_INIT 0x668
#define PHB_PCIE_UTL_CONFIG 0x670
#define PHB_PCIE_DLP_CONTROL 0x678
#define PHB_PCIE_UTL_ERRLOG1 0x680
#define PHB_PCIE_UTL_ERRLOG2 0x688
#define PHB_PCIE_UTL_ERRLOG3 0x690
#define PHB_PCIE_UTL_ERRLOG4 0x698
#define PHB_PCIE_DLP_ERRLOG1 0x6a0
#define PHB_PCIE_DLP_ERRLOG2 0x6a8
#define PHB_PCIE_DLP_ERR_STATUS 0x6b0
#define PHB_PCIE_DLP_ERR_COUNTERS 0x6b8
#define PHB_PCIE_UTL_ERR_INJECT 0x6c0
#define PHB_PCIE_TLDLP_ERR_INJECT 0x6c8
#define PHB_PCIE_LANE_EQ_CNTL0 0x6d0
#define PHB_PCIE_LANE_EQ_CNTL1 0x6d8
#define PHB_PCIE_LANE_EQ_CNTL2 0x6e0
#define PHB_PCIE_LANE_EQ_CNTL3 0x6e8
#define PHB_PCIE_STRAPPING 0x700
/* Fundamental register set B */
#define PHB_VERSION 0x800
#define PHB_RESET 0x808
#define PHB_CONTROL 0x810
#define PHB_CTRL_IVE_128_BYTES PPC_BIT(24)
#define PHB_AIB_RX_CRED_INIT_TIMER 0x818
#define PHB_AIB_RX_CMD_CRED 0x820
#define PHB_AIB_RX_DATA_CRED 0x828
#define PHB_AIB_TX_CMD_CRED 0x830
#define PHB_AIB_TX_DATA_CRED 0x838
#define PHB_AIB_TX_CHAN_MAPPING 0x840
#define PHB_AIB_TAG_ENABLE 0x858
#define PHB_AIB_FENCE_CTRL 0x860
#define PHB_TCE_TAG_ENABLE 0x868
#define PHB_TCE_WATERMARK 0x870
#define PHB_TIMEOUT_CTRL1 0x878
#define PHB_TIMEOUT_CTRL2 0x880
#define PHB_Q_DMA_R 0x888
#define PHB_Q_DMA_R_QUIESCE_DMA PPC_BIT(0)
#define PHB_Q_DMA_R_AUTORESET PPC_BIT(1)
#define PHB_Q_DMA_R_DMA_RESP_STATUS PPC_BIT(4)
#define PHB_Q_DMA_R_MMIO_RESP_STATUS PPC_BIT(5)
#define PHB_Q_DMA_R_TCE_RESP_STATUS PPC_BIT(6)
#define PHB_AIB_TAG_STATUS 0x900
#define PHB_TCE_TAG_STATUS 0x908
/* FIR & Error registers */
#define PHB_LEM_FIR_ACCUM 0xc00
#define PHB_LEM_FIR_AND_MASK 0xc08
#define PHB_LEM_FIR_OR_MASK 0xc10
#define PHB_LEM_ERROR_MASK 0xc18
#define PHB_LEM_ERROR_AND_MASK 0xc20
#define PHB_LEM_ERROR_OR_MASK 0xc28
#define PHB_LEM_ACTION0 0xc30
#define PHB_LEM_ACTION1 0xc38
#define PHB_LEM_WOF 0xc40
#define PHB_ERR_STATUS 0xc80
#define PHB_ERR1_STATUS 0xc88
#define PHB_ERR_INJECT 0xc90
#define PHB_ERR_LEM_ENABLE 0xc98
#define PHB_ERR_IRQ_ENABLE 0xca0
#define PHB_ERR_FREEZE_ENABLE 0xca8
#define PHB_ERR_AIB_FENCE_ENABLE 0xcb0
#define PHB_ERR_LOG_0 0xcc0
#define PHB_ERR_LOG_1 0xcc8
#define PHB_ERR_STATUS_MASK 0xcd0
#define PHB_ERR1_STATUS_MASK 0xcd8
#define PHB_OUT_ERR_STATUS 0xd00
#define PHB_OUT_ERR1_STATUS 0xd08
#define PHB_OUT_ERR_INJECT 0xd10
#define PHB_OUT_ERR_LEM_ENABLE 0xd18
#define PHB_OUT_ERR_IRQ_ENABLE 0xd20
#define PHB_OUT_ERR_FREEZE_ENABLE 0xd28
#define PHB_OUT_ERR_AIB_FENCE_ENABLE 0xd30
#define PHB_OUT_ERR_LOG_0 0xd40
#define PHB_OUT_ERR_LOG_1 0xd48
#define PHB_OUT_ERR_STATUS_MASK 0xd50
#define PHB_OUT_ERR1_STATUS_MASK 0xd58
#define PHB_INA_ERR_STATUS 0xd80
#define PHB_INA_ERR1_STATUS 0xd88
#define PHB_INA_ERR_INJECT 0xd90
#define PHB_INA_ERR_LEM_ENABLE 0xd98
#define PHB_INA_ERR_IRQ_ENABLE 0xda0
#define PHB_INA_ERR_FREEZE_ENABLE 0xda8
#define PHB_INA_ERR_AIB_FENCE_ENABLE 0xdb0
#define PHB_INA_ERR_LOG_0 0xdc0
#define PHB_INA_ERR_LOG_1 0xdc8
#define PHB_INA_ERR_STATUS_MASK 0xdd0
#define PHB_INA_ERR1_STATUS_MASK 0xdd8
#define PHB_INB_ERR_STATUS 0xe00
#define PHB_INB_ERR1_STATUS 0xe08
#define PHB_INB_ERR_INJECT 0xe10
#define PHB_INB_ERR_LEM_ENABLE 0xe18
#define PHB_INB_ERR_IRQ_ENABLE 0xe20
#define PHB_INB_ERR_FREEZE_ENABLE 0xe28
#define PHB_INB_ERR_AIB_FENCE_ENABLE 0xe30
#define PHB_INB_ERR_LOG_0 0xe40
#define PHB_INB_ERR_LOG_1 0xe48
#define PHB_INB_ERR_STATUS_MASK 0xe50
#define PHB_INB_ERR1_STATUS_MASK 0xe58
/* Performance monitor & Debug registers */
#define PHB_TRACE_CONTROL 0xf80
#define PHB_PERFMON_CONFIG 0xf88
#define PHB_PERFMON_CTR0 0xf90
#define PHB_PERFMON_CTR1 0xf98
#define PHB_PERFMON_CTR2 0xfa0
#define PHB_PERFMON_CTR3 0xfa8
#define PHB_HOTPLUG_OVERRIDE 0xfb0
#define PHB_HPOVR_FORCE_RESAMPLE PPC_BIT(9)
#define PHB_HPOVR_PRESENCE_A PPC_BIT(10)
#define PHB_HPOVR_PRESENCE_B PPC_BIT(11)
#define PHB_HPOVR_LINK_ACTIVE PPC_BIT(12)
#define PHB_HPOVR_LINK_BIFURCATED PPC_BIT(13)
#define PHB_HPOVR_LINK_LANE_SWAPPED PPC_BIT(14)
/*
* IODA2 on-chip tables
*/
#define IODA2_TBL_LIST 1
#define IODA2_TBL_LXIVT 2
#define IODA2_TBL_IVC_CAM 3
#define IODA2_TBL_RBA 4
#define IODA2_TBL_RCAM 5
#define IODA2_TBL_MRT 6
#define IODA2_TBL_PESTA 7
#define IODA2_TBL_PESTB 8
#define IODA2_TBL_TVT 9
#define IODA2_TBL_TCAM 10
#define IODA2_TBL_TDR 11
#define IODA2_TBL_M64BT 16
#define IODA2_TBL_M32DT 17
#define IODA2_TBL_PEEV 20
/* LXIVT */
#define IODA2_LXIVT_SERVER PPC_BITMASK(8, 23)
#define IODA2_LXIVT_PRIORITY PPC_BITMASK(24, 31)
#define IODA2_LXIVT_NODE_ID PPC_BITMASK(56, 63)
/* IVT */
#define IODA2_IVT_SERVER PPC_BITMASK(0, 23)
#define IODA2_IVT_PRIORITY PPC_BITMASK(24, 31)
#define IODA2_IVT_GEN PPC_BITMASK(37, 38)
#define IODA2_IVT_P PPC_BITMASK(39, 39)
#define IODA2_IVT_Q PPC_BITMASK(47, 47)
#define IODA2_IVT_PE PPC_BITMASK(48, 63)
/* TVT */
#define IODA2_TVT_TABLE_ADDR PPC_BITMASK(0, 47)
#define IODA2_TVT_NUM_LEVELS PPC_BITMASK(48, 50)
#define IODA2_TVE_1_LEVEL 0
#define IODA2_TVE_2_LEVELS 1
#define IODA2_TVE_3_LEVELS 2
#define IODA2_TVE_4_LEVELS 3
#define IODA2_TVE_5_LEVELS 4
#define IODA2_TVT_TCE_TABLE_SIZE PPC_BITMASK(51, 55)
#define IODA2_TVT_IO_PSIZE PPC_BITMASK(59, 63)
/* PESTA */
#define IODA2_PESTA_MMIO_FROZEN PPC_BIT(0)
/* PESTB */
#define IODA2_PESTB_DMA_STOPPED PPC_BIT(0)
/* M32DT */
#define IODA2_M32DT_PE PPC_BITMASK(8, 15)
/* M64BT */
#define IODA2_M64BT_ENABLE PPC_BIT(0)
#define IODA2_M64BT_SINGLE_PE PPC_BIT(1)
#define IODA2_M64BT_BASE PPC_BITMASK(2, 31)
#define IODA2_M64BT_MASK PPC_BITMASK(34, 63)
#define IODA2_M64BT_SINGLE_BASE PPC_BITMASK(2, 26)
#define IODA2_M64BT_PE_HI PPC_BITMASK(27, 31)
#define IODA2_M64BT_SINGLE_MASK PPC_BITMASK(34, 58)
#define IODA2_M64BT_PE_LOW PPC_BITMASK(59, 63)
/*
* IODA2 in-memory tables
*/
/*
* PEST
*
* 2x8 bytes entries, PEST0 and PEST1
*/
#define IODA2_PEST0_MMIO_CAUSE PPC_BIT(2)
#define IODA2_PEST0_CFG_READ PPC_BIT(3)
#define IODA2_PEST0_CFG_WRITE PPC_BIT(4)
#define IODA2_PEST0_TTYPE PPC_BITMASK(5, 7)
#define PEST_TTYPE_DMA_WRITE 0
#define PEST_TTYPE_MSI 1
#define PEST_TTYPE_DMA_READ 2
#define PEST_TTYPE_DMA_READ_RESP 3
#define PEST_TTYPE_MMIO_LOAD 4
#define PEST_TTYPE_MMIO_STORE 5
#define PEST_TTYPE_OTHER 7
#define IODA2_PEST0_CA_RETURN PPC_BIT(8)
#define IODA2_PEST0_UTL_RTOS_TIMEOUT PPC_BIT(8) /* Same bit as CA return */
#define IODA2_PEST0_UR_RETURN PPC_BIT(9)
#define IODA2_PEST0_UTL_NONFATAL PPC_BIT(10)
#define IODA2_PEST0_UTL_FATAL PPC_BIT(11)
#define IODA2_PEST0_PARITY_UE PPC_BIT(13)
#define IODA2_PEST0_UTL_CORRECTABLE PPC_BIT(14)
#define IODA2_PEST0_UTL_INTERRUPT PPC_BIT(15)
#define IODA2_PEST0_MMIO_XLATE PPC_BIT(16)
#define IODA2_PEST0_IODA2_ERROR PPC_BIT(16) /* Same bit as MMIO xlate */
#define IODA2_PEST0_TCE_PAGE_FAULT PPC_BIT(18)
#define IODA2_PEST0_TCE_ACCESS_FAULT PPC_BIT(19)
#define IODA2_PEST0_DMA_RESP_TIMEOUT PPC_BIT(20)
#define IODA2_PEST0_AIB_SIZE_INVALID PPC_BIT(21)
#define IODA2_PEST0_LEM_BIT PPC_BITMASK(26, 31)
#define IODA2_PEST0_RID PPC_BITMASK(32, 47)
#define IODA2_PEST0_MSI_DATA PPC_BITMASK(48, 63)
#define IODA2_PEST1_FAIL_ADDR PPC_BITMASK(3, 63)
#endif /* PCI_HOST_PNV_PHB3_REGS_H */

4
include/hw/ppc/pnv.h
View File

@ -30,6 +30,7 @@
#include "hw/ppc/pnv_homer.h"
#include "hw/ppc/pnv_xive.h"
#include "hw/ppc/pnv_core.h"
#include "hw/pci-host/pnv_phb3.h"
#include "hw/pci-host/pnv_phb4.h"
#define TYPE_PNV_CHIP "pnv-chip"
@ -77,6 +78,9 @@ typedef struct Pnv8Chip {
PnvOCC occ;
PnvHomer homer;
#define PNV8_CHIP_PHB3_MAX 4
PnvPHB3 phbs[PNV8_CHIP_PHB3_MAX];
XICSFabric *xics;
} Pnv8Chip;

9
include/hw/ppc/pnv_xscom.h
View File

@ -71,6 +71,15 @@ typedef struct PnvXScomInterfaceClass {
#define PNV_XSCOM_PBA_BASE 0x2013f00
#define PNV_XSCOM_PBA_SIZE 0x40
#define PNV_XSCOM_PBCQ_NEST_BASE 0x2012000
#define PNV_XSCOM_PBCQ_NEST_SIZE 0x46
#define PNV_XSCOM_PBCQ_PCI_BASE 0x9012000
#define PNV_XSCOM_PBCQ_PCI_SIZE 0x15
#define PNV_XSCOM_PBCQ_SPCI_BASE 0x9013c00
#define PNV_XSCOM_PBCQ_SPCI_SIZE 0x5
/*
* Layout of the XSCOM PCB addresses (POWER 9)
*/

5
include/hw/ppc/xics.h
View File

@ -101,6 +101,10 @@ struct ICSStateClass {
DeviceClass parent_class;
DeviceRealize parent_realize;
DeviceReset parent_reset;
void (*reject)(ICSState *s, uint32_t irq);
void (*resend)(ICSState *s);
};
struct ICSState {
@ -161,6 +165,7 @@ void icp_set_mfrr(ICPState *icp, uint8_t mfrr);
uint32_t icp_accept(ICPState *ss);
uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr);
void icp_eoi(ICPState *icp, uint32_t xirr);
void icp_irq(ICSState *ics, int server, int nr, uint8_t priority);
void icp_reset(ICPState *icp);
void ics_write_xive(ICSState *ics, int nr, int server,