mirror of
https://github.com/qemu/qemu.git
synced 2024-11-24 19:33:39 +08:00
strongarm: mask off high[31:28] bits from dir and state registers
The high[31:28] bits of 'direction' and 'state' registers of SA-1100/SA-1110 device are reserved. Setting them may lead to OOB 's->handler[]' array access issue. Mask off [31:28] bits to avoid it. Reported-by: Moguofang <moguofang@huawei.com> Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org> Message-id: 20181030114635.31232-1-ppandit@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
parent
22461bd2e5
commit
9a93b2fa0e
@ -587,12 +587,12 @@ static void strongarm_gpio_write(void *opaque, hwaddr offset,
|
||||
|
||||
switch (offset) {
|
||||
case GPDR: /* GPIO Pin-Direction registers */
|
||||
s->dir = value;
|
||||
s->dir = value & 0x0fffffff;
|
||||
strongarm_gpio_handler_update(s);
|
||||
break;
|
||||
|
||||
case GPSR: /* GPIO Pin-Output Set registers */
|
||||
s->olevel |= value;
|
||||
s->olevel |= value & 0x0fffffff;
|
||||
strongarm_gpio_handler_update(s);
|
||||
break;
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user