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vmstate: port pxa2xx_lcd
Signed-off-by: Juan Quintela <quintela@redhat.com>
This commit is contained in:
parent
469954090f
commit
99838363ba
110
hw/pxa2xx_lcd.c
110
hw/pxa2xx_lcd.c
@ -833,74 +833,26 @@ static void pxa2xx_lcdc_orientation(void *opaque, int angle)
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pxa2xx_lcdc_resize(s);
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}
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static void pxa2xx_lcdc_save(QEMUFile *f, void *opaque)
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{
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PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
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int i;
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qemu_put_be32(f, s->irqlevel);
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qemu_put_be32(f, s->transp);
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for (i = 0; i < 6; i ++)
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qemu_put_be32s(f, &s->control[i]);
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for (i = 0; i < 2; i ++)
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qemu_put_be32s(f, &s->status[i]);
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for (i = 0; i < 2; i ++)
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qemu_put_be32s(f, &s->ovl1c[i]);
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for (i = 0; i < 2; i ++)
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qemu_put_be32s(f, &s->ovl2c[i]);
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qemu_put_be32s(f, &s->ccr);
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qemu_put_be32s(f, &s->cmdcr);
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qemu_put_be32s(f, &s->trgbr);
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qemu_put_be32s(f, &s->tcr);
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qemu_put_be32s(f, &s->liidr);
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qemu_put_8s(f, &s->bscntr);
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for (i = 0; i < 7; i ++) {
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qemu_put_betl(f, s->dma_ch[i].branch);
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qemu_put_byte(f, s->dma_ch[i].up);
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qemu_put_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));
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qemu_put_betl(f, s->dma_ch[i].descriptor);
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qemu_put_betl(f, s->dma_ch[i].source);
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qemu_put_be32s(f, &s->dma_ch[i].id);
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qemu_put_be32s(f, &s->dma_ch[i].command);
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static const VMStateDescription vmstate_dma_channel = {
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.name = "dma_channel",
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.version_id = 0,
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.minimum_version_id = 0,
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.minimum_version_id_old = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINTTL(branch, struct DMAChannel),
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VMSTATE_UINT8(up, struct DMAChannel),
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VMSTATE_BUFFER(pbuffer, struct DMAChannel),
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VMSTATE_UINTTL(descriptor, struct DMAChannel),
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VMSTATE_UINTTL(source, struct DMAChannel),
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VMSTATE_UINT32(id, struct DMAChannel),
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VMSTATE_UINT32(command, struct DMAChannel),
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VMSTATE_END_OF_LIST()
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}
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}
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};
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static int pxa2xx_lcdc_load(QEMUFile *f, void *opaque, int version_id)
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static int pxa2xx_lcdc_post_load(void *opaque, int version_id)
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{
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PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
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int i;
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s->irqlevel = qemu_get_be32(f);
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s->transp = qemu_get_be32(f);
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for (i = 0; i < 6; i ++)
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qemu_get_be32s(f, &s->control[i]);
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for (i = 0; i < 2; i ++)
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qemu_get_be32s(f, &s->status[i]);
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for (i = 0; i < 2; i ++)
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qemu_get_be32s(f, &s->ovl1c[i]);
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for (i = 0; i < 2; i ++)
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qemu_get_be32s(f, &s->ovl2c[i]);
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qemu_get_be32s(f, &s->ccr);
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qemu_get_be32s(f, &s->cmdcr);
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qemu_get_be32s(f, &s->trgbr);
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qemu_get_be32s(f, &s->tcr);
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qemu_get_be32s(f, &s->liidr);
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qemu_get_8s(f, &s->bscntr);
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for (i = 0; i < 7; i ++) {
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s->dma_ch[i].branch = qemu_get_betl(f);
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s->dma_ch[i].up = qemu_get_byte(f);
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qemu_get_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));
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s->dma_ch[i].descriptor = qemu_get_betl(f);
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s->dma_ch[i].source = qemu_get_betl(f);
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qemu_get_be32s(f, &s->dma_ch[i].id);
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qemu_get_be32s(f, &s->dma_ch[i].command);
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}
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PXA2xxLCDState *s = opaque;
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s->bpp = LCCR3_BPP(s->control[3]);
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s->xres = s->yres = s->pal_for = -1;
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@ -908,6 +860,31 @@ static int pxa2xx_lcdc_load(QEMUFile *f, void *opaque, int version_id)
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return 0;
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}
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static const VMStateDescription vmstate_pxa2xx_lcdc = {
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.name = "pxa2xx_lcdc",
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.version_id = 0,
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.minimum_version_id = 0,
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.minimum_version_id_old = 0,
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.post_load = pxa2xx_lcdc_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_INT32(irqlevel, PXA2xxLCDState),
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VMSTATE_INT32(transp, PXA2xxLCDState),
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VMSTATE_UINT32_ARRAY(control, PXA2xxLCDState, 6),
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VMSTATE_UINT32_ARRAY(status, PXA2xxLCDState, 2),
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VMSTATE_UINT32_ARRAY(ovl1c, PXA2xxLCDState, 2),
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VMSTATE_UINT32_ARRAY(ovl2c, PXA2xxLCDState, 2),
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VMSTATE_UINT32(ccr, PXA2xxLCDState),
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VMSTATE_UINT32(cmdcr, PXA2xxLCDState),
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VMSTATE_UINT32(trgbr, PXA2xxLCDState),
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VMSTATE_UINT32(tcr, PXA2xxLCDState),
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VMSTATE_UINT32(liidr, PXA2xxLCDState),
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VMSTATE_UINT8(bscntr, PXA2xxLCDState),
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VMSTATE_STRUCT_ARRAY(dma_ch, PXA2xxLCDState, 7, 0,
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vmstate_dma_channel, struct DMAChannel),
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VMSTATE_END_OF_LIST()
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}
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};
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#define BITS 8
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#include "pxa2xx_template.h"
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#define BITS 15
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@ -972,8 +949,7 @@ PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq)
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exit(1);
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}
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register_savevm(NULL, "pxa2xx_lcdc", 0, 0,
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pxa2xx_lcdc_save, pxa2xx_lcdc_load, s);
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vmstate_register(NULL, 0, &vmstate_pxa2xx_lcdc, s);
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return s;
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}
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