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ETRAX-PIC: Untabify.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
Edgar E. Iglesias
parent
3b1fd90ed1
commit
979d98ca90
168
hw/etraxfs_pic.c
168
hw/etraxfs_pic.c
@ -29,85 +29,85 @@
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#define D(x)
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#define R_RW_MASK 0
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#define R_R_VECT 1
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#define R_R_MASKED_VECT 2
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#define R_R_NMI 3
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#define R_R_GURU 4
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#define R_MAX 5
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#define R_RW_MASK 0
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#define R_R_VECT 1
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#define R_R_MASKED_VECT 2
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#define R_R_NMI 3
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#define R_R_GURU 4
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#define R_MAX 5
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struct fs_pic_state
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{
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CPUState *env;
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uint32_t regs[R_MAX];
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CPUState *env;
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uint32_t regs[R_MAX];
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};
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static void pic_update(struct fs_pic_state *fs)
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{
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CPUState *env = fs->env;
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uint32_t vector = 0;
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int i;
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{
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CPUState *env = fs->env;
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uint32_t vector = 0;
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int i;
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fs->regs[R_R_MASKED_VECT] = fs->regs[R_R_VECT] & fs->regs[R_RW_MASK];
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fs->regs[R_R_MASKED_VECT] = fs->regs[R_R_VECT] & fs->regs[R_RW_MASK];
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/* The ETRAX interrupt controller signals interrupts to teh core
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through an interrupt request wire and an irq vector bus. If
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multiple interrupts are simultaneously active it chooses vector
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0x30 and lets the sw choose the priorities. */
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if (fs->regs[R_R_MASKED_VECT]) {
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uint32_t mv = fs->regs[R_R_MASKED_VECT];
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for (i = 0; i < 31; i++) {
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if (mv & 1) {
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vector = 0x31 + i;
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/* Check for multiple interrupts. */
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if (mv > 1)
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vector = 0x30;
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break;
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}
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mv >>= 1;
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}
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if (vector) {
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env->interrupt_vector = vector;
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D(printf("%s vector=%x\n", __func__, vector));
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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}
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} else {
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env->interrupt_vector = 0;
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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D(printf("%s reset irqs\n", __func__));
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}
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/* The ETRAX interrupt controller signals interrupts to teh core
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through an interrupt request wire and an irq vector bus. If
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multiple interrupts are simultaneously active it chooses vector
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0x30 and lets the sw choose the priorities. */
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if (fs->regs[R_R_MASKED_VECT]) {
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uint32_t mv = fs->regs[R_R_MASKED_VECT];
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for (i = 0; i < 31; i++) {
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if (mv & 1) {
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vector = 0x31 + i;
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/* Check for multiple interrupts. */
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if (mv > 1)
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vector = 0x30;
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break;
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}
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mv >>= 1;
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}
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if (vector) {
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env->interrupt_vector = vector;
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D(printf("%s vector=%x\n", __func__, vector));
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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}
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} else {
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env->interrupt_vector = 0;
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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D(printf("%s reset irqs\n", __func__));
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}
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}
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static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
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{
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struct fs_pic_state *fs = opaque;
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uint32_t rval;
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struct fs_pic_state *fs = opaque;
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uint32_t rval;
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rval = fs->regs[addr >> 2];
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D(printf("%s %x=%x\n", __func__, addr, rval));
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return rval;
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rval = fs->regs[addr >> 2];
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D(printf("%s %x=%x\n", __func__, addr, rval));
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return rval;
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}
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static void
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pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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struct fs_pic_state *fs = opaque;
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D(printf("%s addr=%x val=%x\n", __func__, addr, value));
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struct fs_pic_state *fs = opaque;
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D(printf("%s addr=%x val=%x\n", __func__, addr, value));
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if (addr == R_RW_MASK) {
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fs->regs[R_RW_MASK] = value;
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pic_update(fs);
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}
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if (addr == R_RW_MASK) {
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fs->regs[R_RW_MASK] = value;
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pic_update(fs);
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}
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}
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static CPUReadMemoryFunc *pic_read[] = {
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NULL, NULL,
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&pic_readl,
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NULL, NULL,
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&pic_readl,
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};
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static CPUWriteMemoryFunc *pic_write[] = {
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NULL, NULL,
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&pic_writel,
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NULL, NULL,
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&pic_writel,
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};
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void pic_info(Monitor *mon)
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@ -119,47 +119,47 @@ void irq_info(Monitor *mon)
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}
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static void nmi_handler(void *opaque, int irq, int level)
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{
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struct fs_pic_state *fs = (void *)opaque;
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CPUState *env = fs->env;
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uint32_t mask;
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{
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struct fs_pic_state *fs = (void *)opaque;
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CPUState *env = fs->env;
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uint32_t mask;
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mask = 1 << irq;
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if (level)
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fs->regs[R_R_NMI] |= mask;
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else
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fs->regs[R_R_NMI] &= ~mask;
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mask = 1 << irq;
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if (level)
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fs->regs[R_R_NMI] |= mask;
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else
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fs->regs[R_R_NMI] &= ~mask;
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if (fs->regs[R_R_NMI])
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cpu_interrupt(env, CPU_INTERRUPT_NMI);
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else
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cpu_reset_interrupt(env, CPU_INTERRUPT_NMI);
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if (fs->regs[R_R_NMI])
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cpu_interrupt(env, CPU_INTERRUPT_NMI);
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else
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cpu_reset_interrupt(env, CPU_INTERRUPT_NMI);
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}
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static void irq_handler(void *opaque, int irq, int level)
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{
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struct fs_pic_state *fs = (void *)opaque;
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{
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struct fs_pic_state *fs = (void *)opaque;
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if (irq >= 30)
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return nmi_handler(opaque, irq, level);
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if (irq >= 30)
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return nmi_handler(opaque, irq, level);
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irq -= 1;
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fs->regs[R_R_VECT] &= ~(1 << irq);
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fs->regs[R_R_VECT] |= (!!level << irq);
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pic_update(fs);
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irq -= 1;
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fs->regs[R_R_VECT] &= ~(1 << irq);
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fs->regs[R_R_VECT] |= (!!level << irq);
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pic_update(fs);
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}
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qemu_irq *etraxfs_pic_init(CPUState *env, target_phys_addr_t base)
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{
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struct fs_pic_state *fs = NULL;
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qemu_irq *irq;
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int intr_vect_regs;
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struct fs_pic_state *fs = NULL;
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qemu_irq *irq;
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int intr_vect_regs;
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fs = qemu_mallocz(sizeof *fs);
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fs->env = env;
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irq = qemu_allocate_irqs(irq_handler, fs, 32);
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fs = qemu_mallocz(sizeof *fs);
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fs->env = env;
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irq = qemu_allocate_irqs(irq_handler, fs, 32);
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intr_vect_regs = cpu_register_io_memory(0, pic_read, pic_write, fs);
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cpu_register_physical_memory(base, R_MAX * 4, intr_vect_regs);
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return irq;
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intr_vect_regs = cpu_register_io_memory(0, pic_read, pic_write, fs);
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cpu_register_physical_memory(base, R_MAX * 4, intr_vect_regs);
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return irq;
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}
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