mirrors/qemu
0
0
Fork 0
mirror of https://github.com/qemu/qemu.git synced 2024-11-26 04:13:39 +08:00
Code Issues Packages Projects Releases Wiki Activity

target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree

Browse Source 
Move PCPYLD (Parallel Copy Lower Doubleword) and PCPYUD
(Parallel Copy Upper Doubleword) to decodetree. Remove
unnecessary code / comments.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-13-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-02-13 12:04:43 +01:00
parent 5a976c0025
commit 94c882f7d1
3 changed files with 48 additions and 80 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

80
target/mips/translate.c
View File

@ -24062,80 +24062,6 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
* PEXTUW * PEXTUW
*/ */
/*
* PCPYLD rd, rs, rt
*
* Parallel Copy Lower Doubleword
*
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-----------+---------+---------+---------+---------+-----------+
* | MMI | rs | rt | rd | PCPYLD | MMI2 |
* +-----------+---------+---------+---------+---------+-----------+
*/
static void gen_mmi_pcpyld(DisasContext *ctx)
{
uint32_t rs, rt, rd;
uint32_t opcode;
opcode = ctx->opcode;
rs = extract32(opcode, 21, 5);
rt = extract32(opcode, 16, 5);
rd = extract32(opcode, 11, 5);
if (rd == 0) {
/* nop */
} else {
if (rs == 0) {
tcg_gen_movi_i64(cpu_gpr_hi[rd], 0);
} else {
tcg_gen_mov_i64(cpu_gpr_hi[rd], cpu_gpr[rs]);
}
if (rt == 0) {
tcg_gen_movi_i64(cpu_gpr[rd], 0);
} else {
if (rd != rt) {
tcg_gen_mov_i64(cpu_gpr[rd], cpu_gpr[rt]);
}
}
}
}
/*
* PCPYUD rd, rs, rt
*
* Parallel Copy Upper Doubleword
*
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-----------+---------+---------+---------+---------+-----------+
* | MMI | rs | rt | rd | PCPYUD | MMI3 |
* +-----------+---------+---------+---------+---------+-----------+
*/
static void gen_mmi_pcpyud(DisasContext *ctx)
{
uint32_t rs, rt, rd;
uint32_t opcode;
opcode = ctx->opcode;
rs = extract32(opcode, 21, 5);
rt = extract32(opcode, 16, 5);
rd = extract32(opcode, 11, 5);
if (rd == 0) {
/* nop */
} else {
gen_load_gpr_hi(cpu_gpr[rd], rs);
if (rt == 0) {
tcg_gen_movi_i64(cpu_gpr_hi[rd], 0);
} else {
if (rd != rt) {
tcg_gen_mov_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rt]);
}
}
}
}
#endif #endif
static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
@ -24952,9 +24878,6 @@ static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_2_PROT3W: /* TODO: MMI_OPC_2_PROT3W */ case MMI_OPC_2_PROT3W: /* TODO: MMI_OPC_2_PROT3W */
gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI2 */ gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI2 */
break; break;
case MMI_OPC_2_PCPYLD:
gen_mmi_pcpyld(ctx);
break;
default: default:
MIPS_INVAL("TX79 MMI class MMI2"); MIPS_INVAL("TX79 MMI class MMI2");
gen_reserved_instruction(ctx); gen_reserved_instruction(ctx);
@ -24980,9 +24903,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */ case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */
gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI3 */ gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI3 */
break; break;
case MMI_OPC_3_PCPYUD:
gen_mmi_pcpyud(ctx);
break;
default: default:
MIPS_INVAL("TX79 MMI class MMI3"); MIPS_INVAL("TX79 MMI class MMI3");
gen_reserved_instruction(ctx); gen_reserved_instruction(ctx);

6
target/mips/tx79.decode
View File

@ -17,6 +17,7 @@
# Named instruction formats. These are generally used to # Named instruction formats. These are generally used to
# reduce the amount of duplication between instruction patterns. # reduce the amount of duplication between instruction patterns.
@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &rtype sa=0
@rt_rd ...... ..... rt:5 rd:5 ..... ...... &rtype rs=0 sa=0 @rt_rd ...... ..... rt:5 rd:5 ..... ...... &rtype rs=0 sa=0
@rs ...... rs:5 ..... .......... ...... &rtype rt=0 rd=0 sa=0 @rs ...... rs:5 ..... .......... ...... &rtype rt=0 rd=0 sa=0
@rd ...... .......... rd:5 ..... ...... &rtype rs=0 rt=0 sa=0 @rd ...... .......... rd:5 ..... ...... &rtype rs=0 rt=0 sa=0
@ -28,6 +29,11 @@ MTHI1 011100 ..... 0000000000 00000 010001 @rs
MFLO1 011100 0000000000 ..... 00000 010010 @rd MFLO1 011100 0000000000 ..... 00000 010010 @rd
MTLO1 011100 ..... 0000000000 00000 010011 @rs MTLO1 011100 ..... 0000000000 00000 010011 @rs
# MMI2
PCPYLD 011100 ..... ..... ..... 01110 001001 @rs_rt_rd
# MMI3 # MMI3
PCPYUD 011100 ..... ..... ..... 01110 101001 @rs_rt_rd
PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd

42
target/mips/tx79_translate.c
View File

@ -71,3 +71,45 @@ static bool trans_PCPYH(DisasContext *s, arg_rtype *a)
return true; return true;
} }
/* Parallel Copy Lower Doubleword */
static bool trans_PCPYLD(DisasContext *s, arg_rtype *a)
{
if (a->rd == 0) {
/* nop */
return true;
}
if (a->rs == 0) {
tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
} else {
tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr[a->rs]);
}
if (a->rt == 0) {
tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
} else if (a->rd != a->rt) {
tcg_gen_mov_i64(cpu_gpr[a->rd], cpu_gpr[a->rt]);
}
return true;
}
/* Parallel Copy Upper Doubleword */
static bool trans_PCPYUD(DisasContext *s, arg_rtype *a)
{
if (a->rd == 0) {
/* nop */
return true;
}
gen_load_gpr_hi(cpu_gpr[a->rd], a->rs);
if (a->rt == 0) {
tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
} else if (a->rd != a->rt) {
tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt]);
}
return true;
}