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target/mips: Style improvements in mips_malta.c
Fixes mostly errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1566216496-17375-16-git-send-email-aleksandar.markovic@rt-rk.com>
This commit is contained in:
Aleksandar Markovic
parent
6c06ea4cec
commit
94818443cf
@ -60,18 +60,18 @@
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#include "hw/semihosting/semihost.h"
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#include "hw/mips/cps.h"
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#define ENVP_ADDR 0x80002000l
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#define ENVP_NB_ENTRIES 16
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#define ENVP_ENTRY_SIZE 256
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#define ENVP_ADDR 0x80002000l
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#define ENVP_NB_ENTRIES 16
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#define ENVP_ENTRY_SIZE 256
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/* Hardware addresses */
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#define FLASH_ADDRESS 0x1e000000ULL
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#define FPGA_ADDRESS 0x1f000000ULL
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#define RESET_ADDRESS 0x1fc00000ULL
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#define FLASH_ADDRESS 0x1e000000ULL
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#define FPGA_ADDRESS 0x1f000000ULL
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#define RESET_ADDRESS 0x1fc00000ULL
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#define FLASH_SIZE 0x400000
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#define FLASH_SIZE 0x400000
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#define MAX_IDE_BUS 2
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#define MAX_IDE_BUS 2
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typedef struct {
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MemoryRegion iomem;
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@ -117,10 +117,11 @@ static void malta_fpga_update_display(void *opaque)
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MaltaFPGAState *s = opaque;
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for (i = 7 ; i >= 0 ; i--) {
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if (s->leds & (1 << i))
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if (s->leds & (1 << i)) {
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leds_text[i] = '#';
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else
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} else {
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leds_text[i] = ' ';
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}
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}
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leds_text[8] = '\0';
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@ -140,8 +141,6 @@ static void malta_fpga_update_display(void *opaque)
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* Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
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*/
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//~ #define DEBUG
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#if defined(DEBUG)
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# define logout(fmt, ...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
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#else
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@ -156,7 +155,7 @@ struct _eeprom24c0x_t {
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uint8_t scl;
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uint8_t sda;
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uint8_t data;
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//~ uint16_t size;
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/* uint16_t size; */
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uint8_t contents[256];
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};
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@ -164,22 +163,38 @@ typedef struct _eeprom24c0x_t eeprom24c0x_t;
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static eeprom24c0x_t spd_eeprom = {
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.contents = {
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/* 00000000: */ 0x80,0x08,0xFF,0x0D,0x0A,0xFF,0x40,0x00,
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/* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,
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/* 00000010: */ 0x8F,0x04,0x02,0x01,0x01,0x00,0x00,0x00,
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/* 00000018: */ 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0xFF,
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/* 00000020: */ 0x15,0x08,0x15,0x08,0x00,0x00,0x00,0x00,
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/* 00000028: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* 00000030: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* 00000038: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x12,0xD0,
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/* 00000040: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* 00000048: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* 00000050: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* 00000058: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* 00000060: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* 00000068: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* 00000070: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* 00000078: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x64,0xF4,
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/* 00000000: */
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0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00,
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/* 00000008: */
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0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01,
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/* 00000010: */
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0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00,
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/* 00000018: */
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0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF,
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/* 00000020: */
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0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00,
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/* 00000028: */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000030: */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000038: */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0,
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/* 00000040: */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000048: */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000050: */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000058: */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000060: */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000068: */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000070: */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000078: */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4,
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},
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};
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@ -349,7 +364,8 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
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/* SWITCH Register */
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case 0x00200:
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val = 0x00000000; /* All switches closed */
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/* ori a3, a3, low(ram_low_size) */
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val = 0x00000000;
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break;
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/* STATUS Register */
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@ -388,10 +404,11 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
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/* GPINP Register */
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case 0x00a08:
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/* IN = OUT until a real I2C control is implemented */
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if (s->i2csel)
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if (s->i2csel) {
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val = s->i2cout;
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else
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} else {
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val = 0x00;
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}
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break;
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/* I2CINP Register */
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@ -416,8 +433,8 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
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default:
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#if 0
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printf ("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
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addr);
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printf("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
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addr);
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#endif
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break;
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}
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@ -469,8 +486,9 @@ static void malta_fpga_write(void *opaque, hwaddr addr,
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/* SOFTRES Register */
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case 0x00500:
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if (val == 0x42)
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if (val == 0x42) {
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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}
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break;
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/* BRKRES Register */
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@ -503,8 +521,8 @@ static void malta_fpga_write(void *opaque, hwaddr addr,
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default:
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#if 0
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printf ("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
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addr);
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printf("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
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addr);
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#endif
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break;
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}
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@ -563,7 +581,7 @@ static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
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memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga",
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&s->iomem, 0, 0x900);
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memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga",
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&s->iomem, 0xa00, 0x10000-0xa00);
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&s->iomem, 0xa00, 0x10000 - 0xa00);
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memory_region_add_subregion(address_space, base, &s->iomem_lo);
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memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi);
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@ -587,7 +605,7 @@ static void network_init(PCIBus *pci_bus)
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{
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int i;
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for(i = 0; i < nb_nics; i++) {
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for (i = 0; i < nb_nics; i++) {
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NICInfo *nd = &nd_table[i];
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const char *default_devaddr = NULL;
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@ -801,27 +819,28 @@ static void write_bootloader_nanomips(uint8_t *base, int64_t run_addr,
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/* jalrc t8 */
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}
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/* ROM and pseudo bootloader
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The following code implements a very very simple bootloader. It first
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loads the registers a0 to a3 to the values expected by the OS, and
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then jump at the kernel address.
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The bootloader should pass the locations of the kernel arguments and
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environment variables tables. Those tables contain the 32-bit address
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of NULL terminated strings. The environment variables table should be
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terminated by a NULL address.
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For a simpler implementation, the number of kernel arguments is fixed
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to two (the name of the kernel and the command line), and the two
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tables are actually the same one.
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The registers a0 to a3 should contain the following values:
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a0 - number of kernel arguments
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a1 - 32-bit address of the kernel arguments table
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a2 - 32-bit address of the environment variables table
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a3 - RAM size in bytes
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*/
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/*
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* ROM and pseudo bootloader
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*
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* The following code implements a very very simple bootloader. It first
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* loads the registers a0 to a3 to the values expected by the OS, and
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* then jump at the kernel address.
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*
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* The bootloader should pass the locations of the kernel arguments and
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* environment variables tables. Those tables contain the 32-bit address
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* of NULL terminated strings. The environment variables table should be
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* terminated by a NULL address.
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*
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* For a simpler implementation, the number of kernel arguments is fixed
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* to two (the name of the kernel and the command line), and the two
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* tables are actually the same one.
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*
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* The registers a0 to a3 should contain the following values:
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* a0 - number of kernel arguments
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* a1 - 32-bit address of the kernel arguments table
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* a2 - 32-bit address of the environment variables table
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* a3 - RAM size in bytes
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*/
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static void write_bootloader(uint8_t *base, int64_t run_addr,
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int64_t kernel_entry)
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{
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@ -859,14 +878,23 @@ static void write_bootloader(uint8_t *base, int64_t run_addr,
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} else {
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stl_p(p++, 0x24040002); /* addiu a0, zero, 2 */
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}
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stl_p(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); /* lui sp, high(ENVP_ADDR) */
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stl_p(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); /* ori sp, sp, low(ENVP_ADDR) */
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stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */
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stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a1, low(ENVP_ADDR) */
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stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
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stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
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stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16)); /* lui a3, high(ram_low_size) */
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stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff)); /* ori a3, a3, low(ram_low_size) */
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/* lui sp, high(ENVP_ADDR) */
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stl_p(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff));
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/* ori sp, sp, low(ENVP_ADDR) */
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stl_p(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff));
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/* lui a1, high(ENVP_ADDR) */
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stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff));
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/* ori a1, a1, low(ENVP_ADDR) */
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stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff));
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/* lui a2, high(ENVP_ADDR + 8) */
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stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff));
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/* ori a2, a2, low(ENVP_ADDR + 8) */
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stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff));
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/* lui a3, high(ram_low_size) */
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stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16));
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/* ori a3, a3, low(ram_low_size) */
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stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff));
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/* Load BAR registers as done by YAMON */
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stl_p(p++, 0x3c09b400); /* lui t1, 0xb400 */
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@ -970,14 +998,15 @@ static void write_bootloader(uint8_t *base, int64_t run_addr,
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}
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static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
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static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf, int index,
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const char *string, ...)
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{
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va_list ap;
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int32_t table_addr;
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if (index >= ENVP_NB_ENTRIES)
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if (index >= ENVP_NB_ENTRIES) {
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return;
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}
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if (string == NULL) {
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prom_buf[index] = 0;
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@ -993,7 +1022,7 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
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}
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/* Kernel */
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static int64_t load_kernel (void)
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static int64_t load_kernel(void)
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{
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int64_t kernel_entry, kernel_high, initrd_size;
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long kernel_size;
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@ -1041,11 +1070,13 @@ static int64_t load_kernel (void)
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initrd_size = 0;
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initrd_offset = 0;
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if (loaderparams.initrd_filename) {
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initrd_size = get_image_size (loaderparams.initrd_filename);
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initrd_size = get_image_size(loaderparams.initrd_filename);
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if (initrd_size > 0) {
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/* The kernel allocates the bootmap memory in the low memory after
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the initrd. It takes at most 128kiB for 2GB RAM and 4kiB
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pages. */
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/*
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* The kernel allocates the bootmap memory in the low memory after
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* the initrd. It takes at most 128kiB for 2GB RAM and 4kiB
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* pages.
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*/
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initrd_offset = (loaderparams.ram_low_size - initrd_size
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- (128 * KiB)
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- ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK;
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@ -1071,9 +1102,10 @@ static int64_t load_kernel (void)
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prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename);
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if (initrd_size > 0) {
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prom_set(prom_buf, prom_index++, "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
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xlate_to_kseg0(NULL, initrd_offset), initrd_size,
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loaderparams.kernel_cmdline);
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prom_set(prom_buf, prom_index++,
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"rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
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xlate_to_kseg0(NULL, initrd_offset),
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initrd_size, loaderparams.kernel_cmdline);
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} else {
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prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline);
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}
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@ -1113,9 +1145,11 @@ static void main_cpu_reset(void *opaque)
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cpu_reset(CPU(cpu));
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/* The bootloader does not need to be rewritten as it is located in a
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read only location. The kernel location and the arguments table
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location does not change. */
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/*
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* The bootloader does not need to be rewritten as it is located in a
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* read only location. The kernel location and the arguments table
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* location does not change.
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*/
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if (loaderparams.kernel_filename) {
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env->CP0_Status &= ~(1 << CP0St_ERL);
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}
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@ -1213,9 +1247,11 @@ void mips_malta_init(MachineState *machine)
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DeviceState *dev = qdev_create(NULL, TYPE_MIPS_MALTA);
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MaltaState *s = MIPS_MALTA(dev);
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/* The whole address space decoded by the GT-64120A doesn't generate
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exception when accessing invalid memory. Create an empty slot to
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emulate this feature. */
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/*
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* The whole address space decoded by the GT-64120A doesn't generate
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* exception when accessing invalid memory. Create an empty slot to
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* emulate this feature.\
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*/
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empty_slot_init(0, 0x20000000);
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qdev_init_nofail(dev);
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@ -1331,8 +1367,10 @@ void mips_malta_init(MachineState *machine)
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exit(1);
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}
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}
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/* In little endian mode the 32bit words in the bios are swapped,
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a neat trick which allows bi-endian firmware. */
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/*
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* In little endian mode the 32bit words in the bios are swapped,
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* a neat trick which allows bi-endian firmware.
|
||||
*/
|
||||
#ifndef TARGET_WORDS_BIGENDIAN
|
||||
{
|
||||
uint32_t *end, *addr;
|
||||
@ -1386,8 +1424,10 @@ void mips_malta_init(MachineState *machine)
|
||||
|
||||
piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
|
||||
|
||||
/* Interrupt controller */
|
||||
/* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
|
||||
/*
|
||||
* Interrupt controller
|
||||
* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
|
||||
*/
|
||||
s->i8259 = i8259_init(isa_bus, i8259_irq);
|
||||
|
||||
isa_bus_irqs(isa_bus, s->i8259);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user