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hw/arm/smmu-common: VMSAv8-64 page table walk
This patch implements the page table walk for VMSAv8-64. Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com> Message-id: 1524665762-31355-4-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Eric Auger
Peter Maydell
parent
cac994ef43
commit
93641948d4
@ -27,6 +27,228 @@
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#include "qemu/error-report.h"
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#include "hw/arm/smmu-common.h"
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#include "smmu-internal.h"
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/* VMSAv8-64 Translation */
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/**
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* get_pte - Get the content of a page table entry located at
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* @base_addr[@index]
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*/
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static int get_pte(dma_addr_t baseaddr, uint32_t index, uint64_t *pte,
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SMMUPTWEventInfo *info)
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{
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int ret;
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dma_addr_t addr = baseaddr + index * sizeof(*pte);
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/* TODO: guarantee 64-bit single-copy atomicity */
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ret = dma_memory_read(&address_space_memory, addr,
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(uint8_t *)pte, sizeof(*pte));
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if (ret != MEMTX_OK) {
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info->type = SMMU_PTW_ERR_WALK_EABT;
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info->addr = addr;
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return -EINVAL;
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}
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trace_smmu_get_pte(baseaddr, index, addr, *pte);
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return 0;
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}
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/* VMSAv8-64 Translation Table Format Descriptor Decoding */
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/**
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* get_page_pte_address - returns the L3 descriptor output address,
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* ie. the page frame
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* ARM ARM spec: Figure D4-17 VMSAv8-64 level 3 descriptor format
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*/
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static inline hwaddr get_page_pte_address(uint64_t pte, int granule_sz)
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{
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return PTE_ADDRESS(pte, granule_sz);
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}
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/**
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* get_table_pte_address - return table descriptor output address,
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* ie. address of next level table
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* ARM ARM Figure D4-16 VMSAv8-64 level0, level1, and level 2 descriptor formats
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*/
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static inline hwaddr get_table_pte_address(uint64_t pte, int granule_sz)
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{
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return PTE_ADDRESS(pte, granule_sz);
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}
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/**
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* get_block_pte_address - return block descriptor output address and block size
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* ARM ARM Figure D4-16 VMSAv8-64 level0, level1, and level 2 descriptor formats
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*/
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static inline hwaddr get_block_pte_address(uint64_t pte, int level,
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int granule_sz, uint64_t *bsz)
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{
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int n = (granule_sz - 3) * (4 - level) + 3;
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*bsz = 1 << n;
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return PTE_ADDRESS(pte, n);
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}
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SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova)
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{
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bool tbi = extract64(iova, 55, 1) ? TBI1(cfg->tbi) : TBI0(cfg->tbi);
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uint8_t tbi_byte = tbi * 8;
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if (cfg->tt[0].tsz &&
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!extract64(iova, 64 - cfg->tt[0].tsz, cfg->tt[0].tsz - tbi_byte)) {
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/* there is a ttbr0 region and we are in it (high bits all zero) */
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return &cfg->tt[0];
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} else if (cfg->tt[1].tsz &&
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!extract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte)) {
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/* there is a ttbr1 region and we are in it (high bits all one) */
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return &cfg->tt[1];
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} else if (!cfg->tt[0].tsz) {
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/* ttbr0 region is "everything not in the ttbr1 region" */
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return &cfg->tt[0];
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} else if (!cfg->tt[1].tsz) {
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/* ttbr1 region is "everything not in the ttbr0 region" */
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return &cfg->tt[1];
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}
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/* in the gap between the two regions, this is a Translation fault */
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return NULL;
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}
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/**
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* smmu_ptw_64 - VMSAv8-64 Walk of the page tables for a given IOVA
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* @cfg: translation config
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* @iova: iova to translate
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* @perm: access type
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* @tlbe: IOMMUTLBEntry (out)
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* @info: handle to an error info
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*
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* Return 0 on success, < 0 on error. In case of error, @info is filled
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* and tlbe->perm is set to IOMMU_NONE.
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* Upon success, @tlbe is filled with translated_addr and entry
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* permission rights.
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*/
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static int smmu_ptw_64(SMMUTransCfg *cfg,
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dma_addr_t iova, IOMMUAccessFlags perm,
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IOMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
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{
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dma_addr_t baseaddr, indexmask;
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int stage = cfg->stage;
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SMMUTransTableInfo *tt = select_tt(cfg, iova);
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uint8_t level, granule_sz, inputsize, stride;
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if (!tt || tt->disabled) {
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info->type = SMMU_PTW_ERR_TRANSLATION;
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goto error;
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}
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granule_sz = tt->granule_sz;
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stride = granule_sz - 3;
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inputsize = 64 - tt->tsz;
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level = 4 - (inputsize - 4) / stride;
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indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1;
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baseaddr = extract64(tt->ttb, 0, 48);
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baseaddr &= ~indexmask;
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tlbe->iova = iova;
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tlbe->addr_mask = (1 << granule_sz) - 1;
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while (level <= 3) {
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uint64_t subpage_size = 1ULL << level_shift(level, granule_sz);
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uint64_t mask = subpage_size - 1;
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uint32_t offset = iova_level_offset(iova, inputsize, level, granule_sz);
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uint64_t pte;
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dma_addr_t pte_addr = baseaddr + offset * sizeof(pte);
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uint8_t ap;
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if (get_pte(baseaddr, offset, &pte, info)) {
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goto error;
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}
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trace_smmu_ptw_level(level, iova, subpage_size,
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baseaddr, offset, pte);
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if (is_invalid_pte(pte) || is_reserved_pte(pte, level)) {
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trace_smmu_ptw_invalid_pte(stage, level, baseaddr,
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pte_addr, offset, pte);
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info->type = SMMU_PTW_ERR_TRANSLATION;
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goto error;
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}
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if (is_page_pte(pte, level)) {
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uint64_t gpa = get_page_pte_address(pte, granule_sz);
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ap = PTE_AP(pte);
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if (is_permission_fault(ap, perm)) {
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info->type = SMMU_PTW_ERR_PERMISSION;
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goto error;
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}
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tlbe->translated_addr = gpa + (iova & mask);
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tlbe->perm = PTE_AP_TO_PERM(ap);
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trace_smmu_ptw_page_pte(stage, level, iova,
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baseaddr, pte_addr, pte, gpa);
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return 0;
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}
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if (is_block_pte(pte, level)) {
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uint64_t block_size;
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hwaddr gpa = get_block_pte_address(pte, level, granule_sz,
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&block_size);
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ap = PTE_AP(pte);
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if (is_permission_fault(ap, perm)) {
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info->type = SMMU_PTW_ERR_PERMISSION;
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goto error;
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}
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trace_smmu_ptw_block_pte(stage, level, baseaddr,
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pte_addr, pte, iova, gpa,
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block_size >> 20);
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tlbe->translated_addr = gpa + (iova & mask);
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tlbe->perm = PTE_AP_TO_PERM(ap);
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return 0;
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}
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/* table pte */
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ap = PTE_APTABLE(pte);
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if (is_permission_fault(ap, perm)) {
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info->type = SMMU_PTW_ERR_PERMISSION;
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goto error;
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}
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baseaddr = get_table_pte_address(pte, granule_sz);
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level++;
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}
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info->type = SMMU_PTW_ERR_TRANSLATION;
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error:
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tlbe->perm = IOMMU_NONE;
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return -EINVAL;
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}
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/**
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* smmu_ptw - Walk the page tables for an IOVA, according to @cfg
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*
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* @cfg: translation configuration
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* @iova: iova to translate
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* @perm: tentative access type
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* @tlbe: returned entry
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* @info: ptw event handle
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*
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* return 0 on success
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*/
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inline int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
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IOMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
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{
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if (!cfg->aa64) {
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/*
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* This code path is not entered as we check this while decoding
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* the configuration data in the derived SMMU model.
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*/
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g_assert_not_reached();
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}
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return smmu_ptw_64(cfg, iova, perm, tlbe, info);
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}
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/**
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* The bus number is used for lookup when SID based invalidation occurs.
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99
hw/arm/smmu-internal.h
Normal file
99
hw/arm/smmu-internal.h
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@ -0,0 +1,99 @@
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/*
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* ARM SMMU support - Internal API
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*
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* Copyright (c) 2017 Red Hat, Inc.
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* Copyright (C) 2014-2016 Broadcom Corporation
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* Written by Prem Mallappa, Eric Auger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_ARM_SMMU_INTERNAL_H
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#define HW_ARM_SMMU_INTERNAL_H
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#define TBI0(tbi) ((tbi) & 0x1)
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#define TBI1(tbi) ((tbi) & 0x2 >> 1)
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/* PTE Manipulation */
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#define ARM_LPAE_PTE_TYPE_SHIFT 0
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#define ARM_LPAE_PTE_TYPE_MASK 0x3
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#define ARM_LPAE_PTE_TYPE_BLOCK 1
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#define ARM_LPAE_PTE_TYPE_TABLE 3
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#define ARM_LPAE_L3_PTE_TYPE_RESERVED 1
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#define ARM_LPAE_L3_PTE_TYPE_PAGE 3
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#define ARM_LPAE_PTE_VALID (1 << 0)
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#define PTE_ADDRESS(pte, shift) \
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(extract64(pte, shift, 47 - shift + 1) << shift)
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#define is_invalid_pte(pte) (!(pte & ARM_LPAE_PTE_VALID))
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#define is_reserved_pte(pte, level) \
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((level == 3) && \
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((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_L3_PTE_TYPE_RESERVED))
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#define is_block_pte(pte, level) \
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((level < 3) && \
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((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_PTE_TYPE_BLOCK))
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#define is_table_pte(pte, level) \
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((level < 3) && \
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((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_PTE_TYPE_TABLE))
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#define is_page_pte(pte, level) \
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((level == 3) && \
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((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_L3_PTE_TYPE_PAGE))
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/* access permissions */
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#define PTE_AP(pte) \
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(extract64(pte, 6, 2))
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#define PTE_APTABLE(pte) \
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(extract64(pte, 61, 2))
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/*
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* TODO: At the moment all transactions are considered as privileged (EL1)
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* as IOMMU translation callback does not pass user/priv attributes.
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*/
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#define is_permission_fault(ap, perm) \
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(((perm) & IOMMU_WO) && ((ap) & 0x2))
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#define PTE_AP_TO_PERM(ap) \
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(IOMMU_ACCESS_FLAG(true, !((ap) & 0x2)))
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/* Level Indexing */
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static inline int level_shift(int level, int granule_sz)
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{
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return granule_sz + (3 - level) * (granule_sz - 3);
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}
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static inline uint64_t level_page_mask(int level, int granule_sz)
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{
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return ~(MAKE_64BIT_MASK(0, level_shift(level, granule_sz)));
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}
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static inline
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uint64_t iova_level_offset(uint64_t iova, int inputsize,
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int level, int gsz)
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{
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return ((iova & MAKE_64BIT_MASK(0, inputsize)) >> level_shift(level, gsz)) &
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MAKE_64BIT_MASK(0, gsz - 3);
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}
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#endif
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@ -4,4 +4,11 @@
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virt_acpi_setup(void) "No fw cfg or ACPI disabled. Bailing out."
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# hw/arm/smmu-common.c
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smmu_add_mr(const char *name) "%s"
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smmu_add_mr(const char *name) "%s"
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smmu_page_walk(int stage, uint64_t baseaddr, int first_level, uint64_t start, uint64_t end) "stage=%d, baseaddr=0x%"PRIx64", first level=%d, start=0x%"PRIx64", end=0x%"PRIx64
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smmu_lookup_table(int level, uint64_t baseaddr, int granule_sz, uint64_t start, uint64_t end, int flags, uint64_t subpage_size) "level=%d baseaddr=0x%"PRIx64" granule=%d, start=0x%"PRIx64" end=0x%"PRIx64" flags=%d subpage_size=0x%"PRIx64
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smmu_ptw_level(int level, uint64_t iova, size_t subpage_size, uint64_t baseaddr, uint32_t offset, uint64_t pte) "level=%d iova=0x%"PRIx64" subpage_sz=0x%zx baseaddr=0x%"PRIx64" offset=%d => pte=0x%"PRIx64
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smmu_ptw_invalid_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint32_t offset, uint64_t pte) "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" offset=%d pte=0x%"PRIx64
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smmu_ptw_page_pte(int stage, int level, uint64_t iova, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t address) "stage=%d level=%d iova=0x%"PRIx64" base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" page address = 0x%"PRIx64
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smmu_ptw_block_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t iova, uint64_t gpa, int bsize_mb) "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" iova=0x%"PRIx64" block address = 0x%"PRIx64" block size = %d MiB"
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smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr, uint64_t pte) "baseaddr=0x%"PRIx64" index=0x%x, pteaddr=0x%"PRIx64", pte=0x%"PRIx64
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@ -128,4 +128,18 @@ static inline uint16_t smmu_get_sid(SMMUDevice *sdev)
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{
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return PCI_BUILD_BDF(pci_bus_num(sdev->bus), sdev->devfn);
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}
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/**
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* smmu_ptw - Perform the page table walk for a given iova / access flags
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* pair, according to @cfg translation config
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*/
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int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
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IOMMUTLBEntry *tlbe, SMMUPTWEventInfo *info);
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/**
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* select_tt - compute which translation table shall be used according to
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* the input iova and translation config and return the TT specific info
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*/
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SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova);
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#endif /* HW_ARM_SMMU_COMMON */
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