mirrors/qemu
0
0
Fork 0
mirror of https://github.com/qemu/qemu.git synced 2024-11-23 19:03:38 +08:00
Code Issues Packages Projects Releases Wiki Activity

target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro

Browse Source 
Replace the boilerplate code to declare CPU QOM types
and macros, and forward-declare the CPU instance type.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220214183144.27402-14-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2022-02-14 17:08:40 +01:00
parent 1ea4a06af0
commit 9295b1aa92
37 changed files with 42 additions and 81 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
include/hw/core/cpu.h
View File

@ -55,6 +55,24 @@ typedef struct CPUClass CPUClass;
DECLARE_CLASS_CHECKERS(CPUClass, CPU,
TYPE_CPU)
/**
* OBJECT_DECLARE_CPU_TYPE:
* @CpuInstanceType: instance struct name
* @CpuClassType: class struct name
* @CPU_MODULE_OBJ_NAME: the CPU name in uppercase with underscore separators
*
* This macro is typically used in "cpu-qom.h" header file, and will:
*
* - create the typedefs for the CPU object and class structs
* - register the type for use with g_autoptr
* - provide three standard type cast functions
*
* The object struct and class struct need to be declared manually.
*/
#define OBJECT_DECLARE_CPU_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME) \
OBJECT_DECLARE_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME); \
typedef CpuInstanceType ArchCPU;
typedef enum MMUAccessType {
MMU_DATA_LOAD = 0,
MMU_DATA_STORE = 1,

3
target/alpha/cpu-qom.h
View File

@ -25,8 +25,7 @@
#define TYPE_ALPHA_CPU "alpha-cpu"
OBJECT_DECLARE_TYPE(AlphaCPU, AlphaCPUClass,
ALPHA_CPU)
OBJECT_DECLARE_CPU_TYPE(AlphaCPU, AlphaCPUClass, ALPHA_CPU)
/**
* AlphaCPUClass:

2
target/alpha/cpu.h
View File

@ -283,8 +283,6 @@ int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
#define cpu_list alpha_cpu_list
typedef AlphaCPU ArchCPU;
#include "exec/cpu-all.h"
enum {

3
target/arm/cpu-qom.h
View File

@ -27,8 +27,7 @@ struct arm_boot_info;
#define TYPE_ARM_CPU "arm-cpu"
OBJECT_DECLARE_TYPE(ARMCPU, ARMCPUClass,
ARM_CPU)
OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU)
#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU

2
target/arm/cpu.h
View File

@ -3410,8 +3410,6 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
}
}
typedef ARMCPU ArchCPU;
#include "exec/cpu-all.h"
/*

3
target/avr/cpu-qom.h
View File

@ -26,8 +26,7 @@
#define TYPE_AVR_CPU "avr-cpu"
OBJECT_DECLARE_TYPE(AVRCPU, AVRCPUClass,
AVR_CPU)
OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU)
/**
* AVRCPUClass:

6
target/avr/cpu.h
View File

@ -143,14 +143,14 @@ typedef struct CPUArchState {
*
* A AVR CPU.
*/
typedef struct AVRCPU {
struct AVRCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPUAVRState env;
} AVRCPU;
};
extern const struct VMStateDescription vms_avr_cpu;
@ -245,8 +245,6 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
typedef AVRCPU ArchCPU;
#include "exec/cpu-all.h"
#endif /* !defined (QEMU_AVR_CPU_H) */

3
target/cris/cpu-qom.h
View File

@ -25,8 +25,7 @@
#define TYPE_CRIS_CPU "cris-cpu"
OBJECT_DECLARE_TYPE(CRISCPU, CRISCPUClass,
CRIS_CPU)
OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU)
/**
* CRISCPUClass:

2
target/cris/cpu.h
View File

@ -265,8 +265,6 @@ static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch)
#define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
#define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
typedef CRISCPU ArchCPU;
#include "exec/cpu-all.h"
static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,

6
target/hexagon/cpu.h
View File

@ -130,7 +130,7 @@ typedef struct CPUArchState {
VTCMStoreLog vtcm_log;
} CPUHexagonState;
OBJECT_DECLARE_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)
OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)
typedef struct HexagonCPUClass {
/*< private >*/
@ -140,7 +140,7 @@ typedef struct HexagonCPUClass {
DeviceReset parent_reset;
} HexagonCPUClass;
typedef struct HexagonCPU {
struct HexagonCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
@ -149,7 +149,7 @@ typedef struct HexagonCPU {
bool lldb_compat;
target_ulong lldb_stack_adjust;
} HexagonCPU;
};
#include "cpu_bits.h"

3
target/hppa/cpu-qom.h
View File

@ -25,8 +25,7 @@
#define TYPE_HPPA_CPU "hppa-cpu"
OBJECT_DECLARE_TYPE(HPPACPU, HPPACPUClass,
HPPA_CPU)
OBJECT_DECLARE_CPU_TYPE(HPPACPU, HPPACPUClass, HPPA_CPU)
/**
* HPPACPUClass:

2
target/hppa/cpu.h
View File

@ -223,8 +223,6 @@ struct HPPACPU {
QEMUTimer *alarm_timer;
};
typedef HPPACPU ArchCPU;
#include "exec/cpu-all.h"
static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)

3
target/i386/cpu-qom.h
View File

@ -30,8 +30,7 @@
#define TYPE_X86_CPU "i386-cpu"
#endif
OBJECT_DECLARE_TYPE(X86CPU, X86CPUClass,
X86_CPU)
OBJECT_DECLARE_CPU_TYPE(X86CPU, X86CPUClass, X86_CPU)
typedef struct X86CPUModel X86CPUModel;

2
target/i386/cpu.h
View File

@ -2074,8 +2074,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *env)
#define CC_SRC2 (env->cc_src2)
#define CC_OP (env->cc_op)
typedef X86CPU ArchCPU;
#include "exec/cpu-all.h"
#include "svm.h"

3
target/m68k/cpu-qom.h
View File

@ -25,8 +25,7 @@
#define TYPE_M68K_CPU "m68k-cpu"
OBJECT_DECLARE_TYPE(M68kCPU, M68kCPUClass,
M68K_CPU)
OBJECT_DECLARE_CPU_TYPE(M68kCPU, M68kCPUClass, M68K_CPU)
/*
* M68kCPUClass:

2
target/m68k/cpu.h
View File

@ -574,8 +574,6 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
typedef M68kCPU ArchCPU;
#include "exec/cpu-all.h"
/* TB flags */

3
target/microblaze/cpu-qom.h
View File

@ -25,8 +25,7 @@
#define TYPE_MICROBLAZE_CPU "microblaze-cpu"
OBJECT_DECLARE_TYPE(MicroBlazeCPU, MicroBlazeCPUClass,
MICROBLAZE_CPU)
OBJECT_DECLARE_CPU_TYPE(MicroBlazeCPU, MicroBlazeCPUClass, MICROBLAZE_CPU)
/**
* MicroBlazeCPUClass:

2
target/microblaze/cpu.h
View File

@ -394,8 +394,6 @@ void mb_tcg_init(void);
#define MMU_USER_IDX 2
/* See NB_MMU_MODES further up the file. */
typedef MicroBlazeCPU ArchCPU;
#include "exec/cpu-all.h"
/* Ensure there is no overlap between the two masks. */

3
target/mips/cpu-qom.h
View File

@ -29,8 +29,7 @@
#define TYPE_MIPS_CPU "mips-cpu"
#endif
OBJECT_DECLARE_TYPE(MIPSCPU, MIPSCPUClass,
MIPS_CPU)
OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
/**
* MIPSCPUClass:

2
target/mips/cpu.h
View File

@ -1217,8 +1217,6 @@ static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
return hflags_mmu_index(env->hflags);
}
typedef MIPSCPU ArchCPU;
#include "exec/cpu-all.h"
/* Exceptions */

3
target/nios2/cpu.h
View File

@ -32,8 +32,7 @@ typedef struct CPUArchState CPUNios2State;
#define TYPE_NIOS2_CPU "nios2-cpu"
OBJECT_DECLARE_TYPE(Nios2CPU, Nios2CPUClass,
NIOS2_CPU)
OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU)
/**
* Nios2CPUClass:

8
target/openrisc/cpu.h
View File

@ -24,13 +24,9 @@
#include "hw/core/cpu.h"
#include "qom/object.h"
/* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */
struct OpenRISCCPU;
#define TYPE_OPENRISC_CPU "or1k-cpu"
OBJECT_DECLARE_TYPE(OpenRISCCPU, OpenRISCCPUClass,
OPENRISC_CPU)
OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
/**
* OpenRISCCPUClass:
@ -348,8 +344,6 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU
typedef OpenRISCCPU ArchCPU;
#include "exec/cpu-all.h"
#define TB_FLAGS_SM SR_SM

3
target/ppc/cpu-qom.h
View File

@ -29,8 +29,7 @@
#define TYPE_POWERPC_CPU "powerpc-cpu"
#endif
OBJECT_DECLARE_TYPE(PowerPCCPU, PowerPCCPUClass,
POWERPC_CPU)
OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU)
typedef struct CPUArchState CPUPPCState;
typedef struct ppc_tb_t ppc_tb_t;

2
target/ppc/cpu.h
View File

@ -1477,8 +1477,6 @@ void ppc_compat_add_property(Object *obj, const char *name,
uint32_t *compat_pvr, const char *basedesc);
#endif /* defined(TARGET_PPC64) */
typedef PowerPCCPU ArchCPU;
#include "exec/cpu-all.h"
/*****************************************************************************/

4
target/riscv/cpu.h
View File

@ -320,8 +320,7 @@ struct CPUArchState {
uint64_t kvm_timer_frequency;
};
OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
RISCV_CPU)
OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
/**
* RISCVCPUClass:
@ -499,7 +498,6 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
#define TB_FLAGS_MSTATUS_VS MSTATUS_VS
typedef RISCVCPU ArchCPU;
#include "exec/cpu-all.h"
FIELD(TB_FLAGS, MEM_IDX, 0, 3)

3
target/rx/cpu-qom.h
View File

@ -26,8 +26,7 @@
#define TYPE_RX62N_CPU RX_CPU_TYPE_NAME("rx62n")
OBJECT_DECLARE_TYPE(RXCPU, RXCPUClass,
RX_CPU)
OBJECT_DECLARE_CPU_TYPE(RXCPU, RXCPUClass, RX_CPU)
/*
* RXCPUClass:

2
target/rx/cpu.h
View File

@ -114,8 +114,6 @@ struct RXCPU {
CPURXState env;
};
typedef RXCPU ArchCPU;
#define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU
#define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_RX_CPU

3
target/s390x/cpu-qom.h
View File

@ -25,8 +25,7 @@
#define TYPE_S390_CPU "s390x-cpu"
OBJECT_DECLARE_TYPE(S390CPU, S390CPUClass,
S390_CPU)
OBJECT_DECLARE_CPU_TYPE(S390CPU, S390CPUClass, S390_CPU)
typedef struct S390CPUModel S390CPUModel;
typedef struct S390CPUDef S390CPUDef;

2
target/s390x/cpu.h
View File

@ -840,8 +840,6 @@ uint64_t s390_cpu_get_psw_mask(CPUS390XState *env);
/* outside of target/s390x/ */
S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
typedef S390CPU ArchCPU;
#include "exec/cpu-all.h"
#endif

3
target/sh4/cpu-qom.h
View File

@ -29,8 +29,7 @@
#define TYPE_SH7751R_CPU SUPERH_CPU_TYPE_NAME("sh7751r")
#define TYPE_SH7785_CPU SUPERH_CPU_TYPE_NAME("sh7785")
OBJECT_DECLARE_TYPE(SuperHCPU, SuperHCPUClass,
SUPERH_CPU)
OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU)
/**
* SuperHCPUClass:

2
target/sh4/cpu.h
View File

@ -264,8 +264,6 @@ static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
}
}
typedef SuperHCPU ArchCPU;
#include "exec/cpu-all.h"
/* MMU control register */

3
target/sparc/cpu-qom.h
View File

@ -29,8 +29,7 @@
#define TYPE_SPARC_CPU "sparc-cpu"
#endif
OBJECT_DECLARE_TYPE(SPARCCPU, SPARCCPUClass,
SPARC_CPU)
OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU)
typedef struct sparc_def_t sparc_def_t;
/**

2
target/sparc/cpu.h
View File

@ -743,8 +743,6 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
#endif
}
typedef SPARCCPU ArchCPU;
#include "exec/cpu-all.h"
#ifdef TARGET_SPARC64

3
target/tricore/cpu-qom.h
View File

@ -24,8 +24,7 @@
#define TYPE_TRICORE_CPU "tricore-cpu"
OBJECT_DECLARE_TYPE(TriCoreCPU, TriCoreCPUClass,
TRICORE_CPU)
OBJECT_DECLARE_CPU_TYPE(TriCoreCPU, TriCoreCPUClass, TRICORE_CPU)
struct TriCoreCPUClass {
/*< private >*/

2
target/tricore/cpu.h
View File

@ -368,8 +368,6 @@ static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch)
return 0;
}
typedef TriCoreCPU ArchCPU;
#include "exec/cpu-all.h"
void cpu_state_reset(CPUTriCoreState *s);

3
target/xtensa/cpu-qom.h
View File

@ -34,8 +34,7 @@
#define TYPE_XTENSA_CPU "xtensa-cpu"
OBJECT_DECLARE_TYPE(XtensaCPU, XtensaCPUClass,
XTENSA_CPU)
OBJECT_DECLARE_CPU_TYPE(XtensaCPU, XtensaCPUClass, XTENSA_CPU)
typedef struct XtensaConfig XtensaConfig;

2
target/xtensa/cpu.h
View File

@ -722,8 +722,6 @@ static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
#define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000
#define XTENSA_CSBASE_LBEG_OFF_SHIFT 16
typedef XtensaCPU ArchCPU;
#include "exec/cpu-all.h"
static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,