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target-microblaze: Introduce a use-pcmp-instr property

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Introduce a use-pcmp-instr property making pcmp instructions
optional.

Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
This commit is contained in:
Edgar E. Iglesias 2017-06-20 13:53:53 +02:00
parent 5683750909
commit 8fc5239e1f
3 changed files with 7 additions and 5 deletions
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5
target/microblaze/cpu.c
View File

@ -157,7 +157,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
| PVR2_D_LMB_MASK \ | PVR2_D_LMB_MASK \
| PVR2_I_OPB_MASK \ | PVR2_I_OPB_MASK \
| PVR2_I_LMB_MASK \ | PVR2_I_LMB_MASK \
| PVR2_USE_PCMP_INSTR \
| PVR2_FPU_EXC_MASK \ | PVR2_FPU_EXC_MASK \
| 0; | 0;
@ -188,7 +187,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
(cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) | (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) |
(cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
(cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) | (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) |
(cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0); (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) |
(cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0);
env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
PVR5_DCACHE_WRITEBACK_MASK : 0; PVR5_DCACHE_WRITEBACK_MASK : 0;
@ -242,6 +242,7 @@ static Property mb_properties[] = {
DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true), DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),
DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true), DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true),
DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true), DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true),
DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true),
DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
false), false),

1
target/microblaze/cpu.h
View File

@ -302,6 +302,7 @@ struct MicroBlazeCPU {
bool use_barrel; bool use_barrel;
bool use_div; bool use_div;
bool use_msr_instr; bool use_msr_instr;
bool use_pcmp_instr;
bool use_mmu; bool use_mmu;
bool dcache_writeback; bool dcache_writeback;
bool endi; bool endi;

6
target/microblaze/translate.c
View File

@ -326,7 +326,7 @@ static void dec_pattern(DisasContext *dc)
if ((dc->tb_flags & MSR_EE_FLAG) if ((dc->tb_flags & MSR_EE_FLAG)
&& (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
&& !((dc->cpu->env.pvr.regs[2] & PVR2_USE_PCMP_INSTR))) { && !dc->cpu->cfg.use_pcmp_instr) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP); t_gen_raise_exception(dc, EXCP_HW_EXCP);
} }
@ -762,11 +762,11 @@ static void dec_bit(DisasContext *dc)
case 0xe0: case 0xe0:
if ((dc->tb_flags & MSR_EE_FLAG) if ((dc->tb_flags & MSR_EE_FLAG)
&& (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
&& !((dc->cpu->env.pvr.regs[2] & PVR2_USE_PCMP_INSTR))) { && !dc->cpu->cfg.use_pcmp_instr) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP); t_gen_raise_exception(dc, EXCP_HW_EXCP);
} }
if (dc->cpu->env.pvr.regs[2] & PVR2_USE_PCMP_INSTR) { if (dc->cpu->cfg.use_pcmp_instr) {
tcg_gen_clzi_i32(cpu_R[dc->rd], cpu_R[dc->ra], 32); tcg_gen_clzi_i32(cpu_R[dc->rd], cpu_R[dc->ra], 32);
} }
break; break;