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spapr: modify the prototype of the cpu_intc_create() method

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Today, the interrupt presenter is linked to a CPU using the
cpu_intc_create() method of the sPAPR IRQ backend. The resulting
object is assigned to the PowerPCCPU 'intc' pointer whatever the
interrupt mode, XICS or XIVE.

To support the 'dual' interrupt mode, we will need to distinguish
between the two presenter objects and for that, we plan to introduce a
second interrupt presenter object pointer under the PowerPCCPU. The
modifications below move the assignment of the presenter object under
the cpu_intc_create() method to prepare ground for the future changes.

Both sPAPR and PowerNV machines are impacted.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Cédric Le Goater 2019-01-02 06:57:34 +01:00 committed by David Gibson
parent a0c493ae67
commit 8fa1f4ef38
6 changed files with 47 additions and 20 deletions
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23
hw/ppc/pnv.c
View File

@ -668,11 +668,20 @@ static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
return (chip->chip_id << 7) | (core_id << 3);
}
static Object *pnv_chip_power8_intc_create(PnvChip *chip, Object *child,
Error **errp)
static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
Error **errp)
{
return icp_create(child, TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()),
errp);
Error *local_err = NULL;
Object *obj;
obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()),
&local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
cpu->intc = obj;
}
/*
@ -690,10 +699,10 @@ static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
return (chip->chip_id << 8) | (core_id << 2);
}
static Object *pnv_chip_power9_intc_create(PnvChip *chip, Object *child,
Error **errp)
static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
Error **errp)
{
return NULL;
return;
}
/* Allowed core identifiers on a POWER8 Processor Chip :

2
hw/ppc/pnv_core.c
View File

@ -114,7 +114,7 @@ static void pnv_realize_vcpu(PowerPCCPU *cpu, PnvChip *chip, Error **errp)
return;
}
cpu->intc = pcc->intc_create(chip, OBJECT(cpu), &local_err);
pcc->intc_create(chip, cpu, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;

2
hw/ppc/spapr_cpu_core.c
View File

@ -232,7 +232,7 @@ static void spapr_realize_vcpu(PowerPCCPU *cpu, sPAPRMachineState *spapr,
qemu_register_reset(spapr_cpu_reset, cpu);
spapr_cpu_reset(cpu);
cpu->intc = spapr->irq->cpu_intc_create(spapr, OBJECT(cpu), &local_err);
spapr->irq->cpu_intc_create(spapr, cpu, &local_err);
if (local_err) {
goto error_unregister;
}

34
hw/ppc/spapr_irq.c
View File

@ -190,10 +190,20 @@ static void spapr_irq_print_info_xics(sPAPRMachineState *spapr, Monitor *mon)
ics_pic_print_info(spapr->ics, mon);
}
static Object *spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr,
Object *cpu, Error **errp)
static void spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr,
PowerPCCPU *cpu, Error **errp)
{
return icp_create(cpu, spapr->icp_type, XICS_FABRIC(spapr), errp);
Error *local_err = NULL;
Object *obj;
obj = icp_create(OBJECT(cpu), spapr->icp_type, XICS_FABRIC(spapr),
&local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
cpu->intc = obj;
}
static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id)
@ -311,17 +321,25 @@ static void spapr_irq_print_info_xive(sPAPRMachineState *spapr,
spapr_xive_pic_print_info(spapr->xive, mon);
}
static Object *spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr,
Object *cpu, Error **errp)
static void spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr,
PowerPCCPU *cpu, Error **errp)
{
Object *obj = xive_tctx_create(cpu, XIVE_ROUTER(spapr->xive), errp);
Error *local_err = NULL;
Object *obj;
obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(spapr->xive), &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
cpu->intc = obj;
/*
* (TCG) Early setting the OS CAM line for hotplugged CPUs as they
* don't benificiate from the reset of the XIVE IRQ backend
* don't beneficiate from the reset of the XIVE IRQ backend
*/
spapr_xive_set_tctx_os_cam(XIVE_TCTX(obj));
return obj;
}
static int spapr_irq_post_load_xive(sPAPRMachineState *spapr, int version_id)

2
include/hw/ppc/pnv.h
View File

@ -98,7 +98,7 @@ typedef struct PnvChipClass {
DeviceRealize parent_realize;
uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
Object *(*intc_create)(PnvChip *chip, Object *child, Error **errp);
void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
ISABus *(*isa_create)(PnvChip *chip, Error **errp);
} PnvChipClass;

4
include/hw/ppc/spapr_irq.h
View File

@ -42,8 +42,8 @@ typedef struct sPAPRIrq {
void (*print_info)(sPAPRMachineState *spapr, Monitor *mon);
void (*dt_populate)(sPAPRMachineState *spapr, uint32_t nr_servers,
void *fdt, uint32_t phandle);
Object *(*cpu_intc_create)(sPAPRMachineState *spapr, Object *cpu,
Error **errp);
void (*cpu_intc_create)(sPAPRMachineState *spapr, PowerPCCPU *cpu,
Error **errp);
int (*post_load)(sPAPRMachineState *spapr, int version_id);
void (*reset)(sPAPRMachineState *spapr, Error **errp);
} sPAPRIrq;