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s390: Add PCI bus support
This patch implements a pci bus for s390x together with infrastructure to generate and handle hotplug events, to configure/unconfigure via sclp instruction, to do iommu translations and provide s390 support for MSI/MSI-X notification processing. Signed-off-by: Frank Blaschka <frank.blaschka@de.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
This commit is contained in:
Frank Blaschka
Cornelia Huck
parent
59ac15326e
commit
8cba80c3a0
@ -538,6 +538,7 @@ S390 Virtio
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M: Alexander Graf <agraf@suse.de>
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S: Maintained
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F: hw/s390x/s390-*.c
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X: hw/s390x/*pci*.[hc]
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S390 Virtio-ccw
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M: Cornelia Huck <cornelia.huck@de.ibm.com>
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@ -548,6 +549,7 @@ F: hw/s390x/s390-virtio-ccw.c
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F: hw/s390x/css.[hc]
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F: hw/s390x/sclp*.[hc]
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F: hw/s390x/ipl*.[hc]
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F: hw/s390x/*pci*.[hc]
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F: include/hw/s390x/
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F: pc-bios/s390-ccw/
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T: git git://github.com/cohuck/qemu virtio-ccw-upstr
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@ -1,3 +1,4 @@
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include pci.mak
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CONFIG_VIRTIO=y
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CONFIG_SCLPCONSOLE=y
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CONFIG_S390_FLIC=y
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@ -8,3 +8,4 @@ obj-y += ipl.o
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obj-y += css.o
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obj-y += s390-virtio-ccw.o
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obj-y += virtio-ccw.o
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obj-y += s390-pci-bus.o
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@ -1299,6 +1299,11 @@ void css_generate_chp_crws(uint8_t cssid, uint8_t chpid)
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/* TODO */
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}
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void css_generate_css_crws(uint8_t cssid)
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{
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css_queue_crw(CRW_RSC_CSS, 0, 0, cssid);
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}
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int css_enable_mcsse(void)
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{
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trace_css_enable_facility("mcsse");
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@ -101,6 +101,7 @@ void css_queue_crw(uint8_t rsc, uint8_t erc, int chain, uint16_t rsid);
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void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid,
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int hotplugged, int add);
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void css_generate_chp_crws(uint8_t cssid, uint8_t chpid);
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void css_generate_css_crws(uint8_t cssid);
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void css_adapter_interrupt(uint8_t isc);
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#define CSS_IO_ADAPTER_VIRTIO 1
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591
hw/s390x/s390-pci-bus.c
Normal file
591
hw/s390x/s390-pci-bus.c
Normal file
@ -0,0 +1,591 @@
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/*
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* s390 PCI BUS
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*
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* Copyright 2014 IBM Corp.
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* Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
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* Hong Bo Li <lihbbj@cn.ibm.com>
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* Yi Min Zhao <zyimin@cn.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or (at
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* your option) any later version. See the COPYING file in the top-level
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* directory.
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*/
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#include "s390-pci-bus.h"
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#include <hw/pci/pci_bus.h>
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#include <hw/pci/msi.h>
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#include <qemu/error-report.h>
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/* #define DEBUG_S390PCI_BUS */
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#ifdef DEBUG_S390PCI_BUS
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#define DPRINTF(fmt, ...) \
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do { fprintf(stderr, "S390pci-bus: " fmt, ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...) \
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do { } while (0)
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#endif
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int chsc_sei_nt2_get_event(void *res)
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{
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ChscSeiNt2Res *nt2_res = (ChscSeiNt2Res *)res;
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PciCcdfAvail *accdf;
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PciCcdfErr *eccdf;
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int rc = 1;
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SeiContainer *sei_cont;
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S390pciState *s = S390_PCI_HOST_BRIDGE(
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object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
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if (!s) {
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return rc;
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}
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sei_cont = QTAILQ_FIRST(&s->pending_sei);
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if (sei_cont) {
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QTAILQ_REMOVE(&s->pending_sei, sei_cont, link);
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nt2_res->nt = 2;
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nt2_res->cc = sei_cont->cc;
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switch (sei_cont->cc) {
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case 1: /* error event */
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eccdf = (PciCcdfErr *)nt2_res->ccdf;
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eccdf->fid = cpu_to_be32(sei_cont->fid);
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eccdf->fh = cpu_to_be32(sei_cont->fh);
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eccdf->e = cpu_to_be32(sei_cont->e);
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eccdf->faddr = cpu_to_be64(sei_cont->faddr);
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eccdf->pec = cpu_to_be16(sei_cont->pec);
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break;
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case 2: /* availability event */
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accdf = (PciCcdfAvail *)nt2_res->ccdf;
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accdf->fid = cpu_to_be32(sei_cont->fid);
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accdf->fh = cpu_to_be32(sei_cont->fh);
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accdf->pec = cpu_to_be16(sei_cont->pec);
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break;
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default:
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abort();
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}
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g_free(sei_cont);
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rc = 0;
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}
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return rc;
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}
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int chsc_sei_nt2_have_event(void)
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{
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S390pciState *s = S390_PCI_HOST_BRIDGE(
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object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
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if (!s) {
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return 0;
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}
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return !QTAILQ_EMPTY(&s->pending_sei);
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}
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S390PCIBusDevice *s390_pci_find_dev_by_fid(uint32_t fid)
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{
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S390PCIBusDevice *pbdev;
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int i;
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S390pciState *s = S390_PCI_HOST_BRIDGE(
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object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
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if (!s) {
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return NULL;
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}
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for (i = 0; i < PCI_SLOT_MAX; i++) {
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pbdev = &s->pbdev[i];
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if ((pbdev->fh != 0) && (pbdev->fid == fid)) {
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return pbdev;
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}
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}
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return NULL;
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}
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void s390_pci_sclp_configure(int configure, SCCB *sccb)
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{
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PciCfgSccb *psccb = (PciCfgSccb *)sccb;
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S390PCIBusDevice *pbdev = s390_pci_find_dev_by_fid(be32_to_cpu(psccb->aid));
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uint16_t rc;
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if (pbdev) {
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if ((configure == 1 && pbdev->configured == true) ||
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(configure == 0 && pbdev->configured == false)) {
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rc = SCLP_RC_NO_ACTION_REQUIRED;
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} else {
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pbdev->configured = !pbdev->configured;
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rc = SCLP_RC_NORMAL_COMPLETION;
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}
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} else {
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DPRINTF("sclp config %d no dev found\n", configure);
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rc = SCLP_RC_ADAPTER_ID_NOT_RECOGNIZED;
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}
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psccb->header.response_code = cpu_to_be16(rc);
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return;
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}
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static uint32_t s390_pci_get_pfid(PCIDevice *pdev)
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{
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return PCI_SLOT(pdev->devfn);
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}
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static uint32_t s390_pci_get_pfh(PCIDevice *pdev)
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{
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return PCI_SLOT(pdev->devfn) | FH_VIRT;
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}
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S390PCIBusDevice *s390_pci_find_dev_by_idx(uint32_t idx)
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{
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S390PCIBusDevice *pbdev;
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int i;
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int j = 0;
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S390pciState *s = S390_PCI_HOST_BRIDGE(
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object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
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if (!s) {
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return NULL;
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}
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for (i = 0; i < PCI_SLOT_MAX; i++) {
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pbdev = &s->pbdev[i];
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if (pbdev->fh == 0) {
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continue;
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}
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if (j == idx) {
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return pbdev;
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}
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j++;
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}
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return NULL;
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}
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S390PCIBusDevice *s390_pci_find_dev_by_fh(uint32_t fh)
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{
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S390PCIBusDevice *pbdev;
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int i;
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S390pciState *s = S390_PCI_HOST_BRIDGE(
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object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
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if (!s) {
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return NULL;
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}
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for (i = 0; i < PCI_SLOT_MAX; i++) {
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pbdev = &s->pbdev[i];
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if (pbdev->fh == fh) {
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return pbdev;
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}
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}
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return NULL;
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}
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static void s390_pci_generate_event(uint8_t cc, uint16_t pec, uint32_t fh,
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uint32_t fid, uint64_t faddr, uint32_t e)
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{
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SeiContainer *sei_cont = g_malloc0(sizeof(SeiContainer));
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S390pciState *s = S390_PCI_HOST_BRIDGE(
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object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
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if (!s) {
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return;
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}
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sei_cont->fh = fh;
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sei_cont->fid = fid;
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sei_cont->cc = cc;
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sei_cont->pec = pec;
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sei_cont->faddr = faddr;
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sei_cont->e = e;
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QTAILQ_INSERT_TAIL(&s->pending_sei, sei_cont, link);
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css_generate_css_crws(0);
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}
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static void s390_pci_generate_plug_event(uint16_t pec, uint32_t fh,
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uint32_t fid)
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{
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s390_pci_generate_event(2, pec, fh, fid, 0, 0);
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}
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static void s390_pci_generate_error_event(uint16_t pec, uint32_t fh,
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uint32_t fid, uint64_t faddr,
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uint32_t e)
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{
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s390_pci_generate_event(1, pec, fh, fid, faddr, e);
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}
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static void s390_pci_set_irq(void *opaque, int irq, int level)
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{
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/* nothing to do */
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}
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static int s390_pci_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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/* nothing to do */
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return 0;
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}
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static uint64_t s390_pci_get_table_origin(uint64_t iota)
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{
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return iota & ~ZPCI_IOTA_RTTO_FLAG;
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}
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static unsigned int calc_rtx(dma_addr_t ptr)
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{
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return ((unsigned long) ptr >> ZPCI_RT_SHIFT) & ZPCI_INDEX_MASK;
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}
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static unsigned int calc_sx(dma_addr_t ptr)
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{
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return ((unsigned long) ptr >> ZPCI_ST_SHIFT) & ZPCI_INDEX_MASK;
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}
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static unsigned int calc_px(dma_addr_t ptr)
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{
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return ((unsigned long) ptr >> PAGE_SHIFT) & ZPCI_PT_MASK;
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}
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static uint64_t get_rt_sto(uint64_t entry)
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{
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return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_RTX)
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? (entry & ZPCI_RTE_ADDR_MASK)
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: 0;
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}
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static uint64_t get_st_pto(uint64_t entry)
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{
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return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_SX)
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? (entry & ZPCI_STE_ADDR_MASK)
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: 0;
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}
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static uint64_t s390_guest_io_table_walk(uint64_t guest_iota,
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uint64_t guest_dma_address)
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{
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uint64_t sto_a, pto_a, px_a;
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uint64_t sto, pto, pte;
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uint32_t rtx, sx, px;
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rtx = calc_rtx(guest_dma_address);
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sx = calc_sx(guest_dma_address);
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px = calc_px(guest_dma_address);
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sto_a = guest_iota + rtx * sizeof(uint64_t);
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sto = ldq_phys(&address_space_memory, sto_a);
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sto = get_rt_sto(sto);
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if (!sto) {
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pte = 0;
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goto out;
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}
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pto_a = sto + sx * sizeof(uint64_t);
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pto = ldq_phys(&address_space_memory, pto_a);
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pto = get_st_pto(pto);
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if (!pto) {
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pte = 0;
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goto out;
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}
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px_a = pto + px * sizeof(uint64_t);
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pte = ldq_phys(&address_space_memory, px_a);
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out:
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return pte;
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}
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static IOMMUTLBEntry s390_translate_iommu(MemoryRegion *iommu, hwaddr addr,
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bool is_write)
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{
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uint64_t pte;
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uint32_t flags;
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S390PCIBusDevice *pbdev = container_of(iommu, S390PCIBusDevice, mr);
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S390pciState *s = S390_PCI_HOST_BRIDGE(pci_device_root_bus(pbdev->pdev)
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->qbus.parent);
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IOMMUTLBEntry ret = {
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.target_as = &address_space_memory,
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.iova = 0,
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.translated_addr = 0,
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.addr_mask = ~(hwaddr)0,
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.perm = IOMMU_NONE,
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};
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DPRINTF("iommu trans addr 0x%" PRIx64 "\n", addr);
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/* s390 does not have an APIC mapped to main storage so we use
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* a separate AddressSpace only for msix notifications
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*/
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if (addr == ZPCI_MSI_ADDR) {
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ret.target_as = &s->msix_notify_as;
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ret.iova = addr;
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ret.translated_addr = addr;
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ret.addr_mask = 0xfff;
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ret.perm = IOMMU_RW;
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return ret;
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}
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if (!pbdev->g_iota) {
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pbdev->error_state = true;
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pbdev->lgstg_blocked = true;
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s390_pci_generate_error_event(ERR_EVENT_INVALAS, pbdev->fh, pbdev->fid,
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addr, 0);
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return ret;
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}
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if (addr < pbdev->pba || addr > pbdev->pal) {
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pbdev->error_state = true;
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pbdev->lgstg_blocked = true;
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s390_pci_generate_error_event(ERR_EVENT_OORANGE, pbdev->fh, pbdev->fid,
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addr, 0);
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return ret;
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}
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pte = s390_guest_io_table_walk(s390_pci_get_table_origin(pbdev->g_iota),
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addr);
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if (!pte) {
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pbdev->error_state = true;
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pbdev->lgstg_blocked = true;
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s390_pci_generate_error_event(ERR_EVENT_SERR, pbdev->fh, pbdev->fid,
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addr, ERR_EVENT_Q_BIT);
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return ret;
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}
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flags = pte & ZPCI_PTE_FLAG_MASK;
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ret.iova = addr;
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ret.translated_addr = pte & ZPCI_PTE_ADDR_MASK;
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ret.addr_mask = 0xfff;
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if (flags & ZPCI_PTE_INVALID) {
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ret.perm = IOMMU_NONE;
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} else {
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ret.perm = IOMMU_RW;
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}
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return ret;
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}
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static const MemoryRegionIOMMUOps s390_iommu_ops = {
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.translate = s390_translate_iommu,
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};
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static AddressSpace *s390_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
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{
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S390pciState *s = opaque;
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return &s->pbdev[PCI_SLOT(devfn)].as;
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}
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static uint8_t set_ind_atomic(uint64_t ind_loc, uint8_t to_be_set)
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{
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uint8_t ind_old, ind_new;
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hwaddr len = 1;
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uint8_t *ind_addr;
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ind_addr = cpu_physical_memory_map(ind_loc, &len, 1);
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if (!ind_addr) {
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s390_pci_generate_error_event(ERR_EVENT_AIRERR, 0, 0, 0, 0);
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return -1;
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}
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do {
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ind_old = *ind_addr;
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ind_new = ind_old | to_be_set;
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} while (atomic_cmpxchg(ind_addr, ind_old, ind_new) != ind_old);
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cpu_physical_memory_unmap(ind_addr, len, 1, len);
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return ind_old;
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}
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|
||||
static void s390_msi_ctrl_write(void *opaque, hwaddr addr, uint64_t data,
|
||||
unsigned int size)
|
||||
{
|
||||
S390PCIBusDevice *pbdev;
|
||||
uint32_t io_int_word;
|
||||
uint32_t fid = data >> ZPCI_MSI_VEC_BITS;
|
||||
uint32_t vec = data & ZPCI_MSI_VEC_MASK;
|
||||
uint64_t ind_bit;
|
||||
uint32_t sum_bit;
|
||||
uint32_t e = 0;
|
||||
|
||||
DPRINTF("write_msix data 0x%" PRIx64 " fid %d vec 0x%x\n", data, fid, vec);
|
||||
|
||||
pbdev = s390_pci_find_dev_by_fid(fid);
|
||||
if (!pbdev) {
|
||||
e |= (vec << ERR_EVENT_MVN_OFFSET);
|
||||
s390_pci_generate_error_event(ERR_EVENT_NOMSI, 0, fid, addr, e);
|
||||
return;
|
||||
}
|
||||
|
||||
ind_bit = pbdev->routes.adapter.ind_offset;
|
||||
sum_bit = pbdev->routes.adapter.summary_offset;
|
||||
|
||||
set_ind_atomic(pbdev->routes.adapter.ind_addr + (ind_bit + vec) / 8,
|
||||
0x80 >> ((ind_bit + vec) % 8));
|
||||
if (!set_ind_atomic(pbdev->routes.adapter.summary_addr + sum_bit / 8,
|
||||
0x80 >> (sum_bit % 8))) {
|
||||
io_int_word = (pbdev->isc << 27) | IO_INT_WORD_AI;
|
||||
s390_io_interrupt(0, 0, 0, io_int_word);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static uint64_t s390_msi_ctrl_read(void *opaque, hwaddr addr, unsigned size)
|
||||
{
|
||||
return 0xffffffff;
|
||||
}
|
||||
|
||||
static const MemoryRegionOps s390_msi_ctrl_ops = {
|
||||
.write = s390_msi_ctrl_write,
|
||||
.read = s390_msi_ctrl_read,
|
||||
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||
};
|
||||
|
||||
static void s390_pcihost_init_as(S390pciState *s)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < PCI_SLOT_MAX; i++) {
|
||||
memory_region_init_iommu(&s->pbdev[i].mr, OBJECT(s),
|
||||
&s390_iommu_ops, "iommu-s390", UINT64_MAX);
|
||||
address_space_init(&s->pbdev[i].as, &s->pbdev[i].mr, "iommu-pci");
|
||||
}
|
||||
|
||||
memory_region_init_io(&s->msix_notify_mr, OBJECT(s),
|
||||
&s390_msi_ctrl_ops, s, "msix-s390", UINT64_MAX);
|
||||
address_space_init(&s->msix_notify_as, &s->msix_notify_mr, "msix-pci");
|
||||
}
|
||||
|
||||
static int s390_pcihost_init(SysBusDevice *dev)
|
||||
{
|
||||
PCIBus *b;
|
||||
BusState *bus;
|
||||
PCIHostState *phb = PCI_HOST_BRIDGE(dev);
|
||||
S390pciState *s = S390_PCI_HOST_BRIDGE(dev);
|
||||
|
||||
DPRINTF("host_init\n");
|
||||
|
||||
b = pci_register_bus(DEVICE(dev), NULL,
|
||||
s390_pci_set_irq, s390_pci_map_irq, NULL,
|
||||
get_system_memory(), get_system_io(), 0, 64,
|
||||
TYPE_PCI_BUS);
|
||||
s390_pcihost_init_as(s);
|
||||
pci_setup_iommu(b, s390_pci_dma_iommu, s);
|
||||
|
||||
bus = BUS(b);
|
||||
qbus_set_hotplug_handler(bus, DEVICE(dev), NULL);
|
||||
phb->bus = b;
|
||||
QTAILQ_INIT(&s->pending_sei);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int s390_pcihost_setup_msix(S390PCIBusDevice *pbdev)
|
||||
{
|
||||
uint8_t pos;
|
||||
uint16_t ctrl;
|
||||
uint32_t table, pba;
|
||||
|
||||
pos = pci_find_capability(pbdev->pdev, PCI_CAP_ID_MSIX);
|
||||
if (!pos) {
|
||||
pbdev->msix.available = false;
|
||||
return 0;
|
||||
}
|
||||
|
||||
ctrl = pci_host_config_read_common(pbdev->pdev, pos + PCI_CAP_FLAGS,
|
||||
pci_config_size(pbdev->pdev), sizeof(ctrl));
|
||||
table = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_TABLE,
|
||||
pci_config_size(pbdev->pdev), sizeof(table));
|
||||
pba = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_PBA,
|
||||
pci_config_size(pbdev->pdev), sizeof(pba));
|
||||
|
||||
pbdev->msix.table_bar = table & PCI_MSIX_FLAGS_BIRMASK;
|
||||
pbdev->msix.table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK;
|
||||
pbdev->msix.pba_bar = pba & PCI_MSIX_FLAGS_BIRMASK;
|
||||
pbdev->msix.pba_offset = pba & ~PCI_MSIX_FLAGS_BIRMASK;
|
||||
pbdev->msix.entries = (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
|
||||
pbdev->msix.available = true;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void s390_pcihost_hot_plug(HotplugHandler *hotplug_dev,
|
||||
DeviceState *dev, Error **errp)
|
||||
{
|
||||
PCIDevice *pci_dev = PCI_DEVICE(dev);
|
||||
S390PCIBusDevice *pbdev;
|
||||
S390pciState *s = S390_PCI_HOST_BRIDGE(pci_device_root_bus(pci_dev)
|
||||
->qbus.parent);
|
||||
|
||||
pbdev = &s->pbdev[PCI_SLOT(pci_dev->devfn)];
|
||||
|
||||
pbdev->fid = s390_pci_get_pfid(pci_dev);
|
||||
pbdev->pdev = pci_dev;
|
||||
pbdev->configured = true;
|
||||
pbdev->fh = s390_pci_get_pfh(pci_dev);
|
||||
|
||||
s390_pcihost_setup_msix(pbdev);
|
||||
|
||||
if (dev->hotplugged) {
|
||||
s390_pci_generate_plug_event(HP_EVENT_RESERVED_TO_STANDBY,
|
||||
pbdev->fh, pbdev->fid);
|
||||
s390_pci_generate_plug_event(HP_EVENT_TO_CONFIGURED,
|
||||
pbdev->fh, pbdev->fid);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
static void s390_pcihost_hot_unplug(HotplugHandler *hotplug_dev,
|
||||
DeviceState *dev, Error **errp)
|
||||
{
|
||||
PCIDevice *pci_dev = PCI_DEVICE(dev);
|
||||
S390pciState *s = S390_PCI_HOST_BRIDGE(pci_device_root_bus(pci_dev)
|
||||
->qbus.parent);
|
||||
S390PCIBusDevice *pbdev = &s->pbdev[PCI_SLOT(pci_dev->devfn)];
|
||||
|
||||
if (pbdev->configured) {
|
||||
pbdev->configured = false;
|
||||
s390_pci_generate_plug_event(HP_EVENT_CONFIGURED_TO_STBRES,
|
||||
pbdev->fh, pbdev->fid);
|
||||
}
|
||||
|
||||
s390_pci_generate_plug_event(HP_EVENT_STANDBY_TO_RESERVED,
|
||||
pbdev->fh, pbdev->fid);
|
||||
pbdev->fh = 0;
|
||||
pbdev->fid = 0;
|
||||
pbdev->pdev = NULL;
|
||||
object_unparent(OBJECT(pci_dev));
|
||||
}
|
||||
|
||||
static void s390_pcihost_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
|
||||
|
||||
dc->cannot_instantiate_with_device_add_yet = true;
|
||||
k->init = s390_pcihost_init;
|
||||
hc->plug = s390_pcihost_hot_plug;
|
||||
hc->unplug = s390_pcihost_hot_unplug;
|
||||
msi_supported = true;
|
||||
}
|
||||
|
||||
static const TypeInfo s390_pcihost_info = {
|
||||
.name = TYPE_S390_PCI_HOST_BRIDGE,
|
||||
.parent = TYPE_PCI_HOST_BRIDGE,
|
||||
.instance_size = sizeof(S390pciState),
|
||||
.class_init = s390_pcihost_class_init,
|
||||
.interfaces = (InterfaceInfo[]) {
|
||||
{ TYPE_HOTPLUG_HANDLER },
|
||||
{ }
|
||||
}
|
||||
};
|
||||
|
||||
static void s390_pci_register_types(void)
|
||||
{
|
||||
type_register_static(&s390_pcihost_info);
|
||||
}
|
||||
|
||||
type_init(s390_pci_register_types)
|
||||
251
hw/s390x/s390-pci-bus.h
Normal file
251
hw/s390x/s390-pci-bus.h
Normal file
@ -0,0 +1,251 @@
|
||||
/*
|
||||
* s390 PCI BUS definitions
|
||||
*
|
||||
* Copyright 2014 IBM Corp.
|
||||
* Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
|
||||
* Hong Bo Li <lihbbj@cn.ibm.com>
|
||||
* Yi Min Zhao <zyimin@cn.ibm.com>
|
||||
*
|
||||
* This work is licensed under the terms of the GNU GPL, version 2 or (at
|
||||
* your option) any later version. See the COPYING file in the top-level
|
||||
* directory.
|
||||
*/
|
||||
|
||||
#ifndef HW_S390_PCI_BUS_H
|
||||
#define HW_S390_PCI_BUS_H
|
||||
|
||||
#include <hw/pci/pci.h>
|
||||
#include <hw/pci/pci_host.h>
|
||||
#include "hw/s390x/sclp.h"
|
||||
#include "hw/s390x/s390_flic.h"
|
||||
#include "hw/s390x/css.h"
|
||||
|
||||
#define TYPE_S390_PCI_HOST_BRIDGE "s390-pcihost"
|
||||
#define FH_VIRT 0x00ff0000
|
||||
#define ENABLE_BIT_OFFSET 31
|
||||
#define S390_PCIPT_ADAPTER 2
|
||||
|
||||
#define S390_PCI_HOST_BRIDGE(obj) \
|
||||
OBJECT_CHECK(S390pciState, (obj), TYPE_S390_PCI_HOST_BRIDGE)
|
||||
|
||||
#define HP_EVENT_TO_CONFIGURED 0x0301
|
||||
#define HP_EVENT_RESERVED_TO_STANDBY 0x0302
|
||||
#define HP_EVENT_CONFIGURED_TO_STBRES 0x0304
|
||||
#define HP_EVENT_STANDBY_TO_RESERVED 0x0308
|
||||
|
||||
#define ERR_EVENT_INVALAS 0x1
|
||||
#define ERR_EVENT_OORANGE 0x2
|
||||
#define ERR_EVENT_INVALTF 0x3
|
||||
#define ERR_EVENT_TPROTE 0x4
|
||||
#define ERR_EVENT_APROTE 0x5
|
||||
#define ERR_EVENT_KEYE 0x6
|
||||
#define ERR_EVENT_INVALTE 0x7
|
||||
#define ERR_EVENT_INVALTL 0x8
|
||||
#define ERR_EVENT_TT 0x9
|
||||
#define ERR_EVENT_INVALMS 0xa
|
||||
#define ERR_EVENT_SERR 0xb
|
||||
#define ERR_EVENT_NOMSI 0x10
|
||||
#define ERR_EVENT_INVALBV 0x11
|
||||
#define ERR_EVENT_AIBV 0x12
|
||||
#define ERR_EVENT_AIRERR 0x13
|
||||
#define ERR_EVENT_FMBA 0x2a
|
||||
#define ERR_EVENT_FMBUP 0x2b
|
||||
#define ERR_EVENT_FMBPRO 0x2c
|
||||
#define ERR_EVENT_CCONF 0x30
|
||||
#define ERR_EVENT_SERVAC 0x3a
|
||||
#define ERR_EVENT_PERMERR 0x3b
|
||||
|
||||
#define ERR_EVENT_Q_BIT 0x2
|
||||
#define ERR_EVENT_MVN_OFFSET 16
|
||||
|
||||
#define ZPCI_MSI_VEC_BITS 11
|
||||
#define ZPCI_MSI_VEC_MASK 0x7ff
|
||||
|
||||
#define ZPCI_MSI_ADDR 0xfe00000000000000ULL
|
||||
#define ZPCI_SDMA_ADDR 0x100000000ULL
|
||||
#define ZPCI_EDMA_ADDR 0x1ffffffffffffffULL
|
||||
|
||||
#define PAGE_SHIFT 12
|
||||
#define PAGE_MASK (~(PAGE_SIZE-1))
|
||||
#define PAGE_DEFAULT_ACC 0
|
||||
#define PAGE_DEFAULT_KEY (PAGE_DEFAULT_ACC << 4)
|
||||
|
||||
/* I/O Translation Anchor (IOTA) */
|
||||
enum ZpciIoatDtype {
|
||||
ZPCI_IOTA_STO = 0,
|
||||
ZPCI_IOTA_RTTO = 1,
|
||||
ZPCI_IOTA_RSTO = 2,
|
||||
ZPCI_IOTA_RFTO = 3,
|
||||
ZPCI_IOTA_PFAA = 4,
|
||||
ZPCI_IOTA_IOPFAA = 5,
|
||||
ZPCI_IOTA_IOPTO = 7
|
||||
};
|
||||
|
||||
#define ZPCI_IOTA_IOT_ENABLED 0x800ULL
|
||||
#define ZPCI_IOTA_DT_ST (ZPCI_IOTA_STO << 2)
|
||||
#define ZPCI_IOTA_DT_RT (ZPCI_IOTA_RTTO << 2)
|
||||
#define ZPCI_IOTA_DT_RS (ZPCI_IOTA_RSTO << 2)
|
||||
#define ZPCI_IOTA_DT_RF (ZPCI_IOTA_RFTO << 2)
|
||||
#define ZPCI_IOTA_DT_PF (ZPCI_IOTA_PFAA << 2)
|
||||
#define ZPCI_IOTA_FS_4K 0
|
||||
#define ZPCI_IOTA_FS_1M 1
|
||||
#define ZPCI_IOTA_FS_2G 2
|
||||
#define ZPCI_KEY (PAGE_DEFAULT_KEY << 5)
|
||||
|
||||
#define ZPCI_IOTA_STO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_ST)
|
||||
#define ZPCI_IOTA_RTTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RT)
|
||||
#define ZPCI_IOTA_RSTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RS)
|
||||
#define ZPCI_IOTA_RFTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RF)
|
||||
#define ZPCI_IOTA_RFAA_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY |\
|
||||
ZPCI_IOTA_DT_PF | ZPCI_IOTA_FS_2G)
|
||||
|
||||
/* I/O Region and segment tables */
|
||||
#define ZPCI_INDEX_MASK 0x7ffULL
|
||||
|
||||
#define ZPCI_TABLE_TYPE_MASK 0xc
|
||||
#define ZPCI_TABLE_TYPE_RFX 0xc
|
||||
#define ZPCI_TABLE_TYPE_RSX 0x8
|
||||
#define ZPCI_TABLE_TYPE_RTX 0x4
|
||||
#define ZPCI_TABLE_TYPE_SX 0x0
|
||||
|
||||
#define ZPCI_TABLE_LEN_RFX 0x3
|
||||
#define ZPCI_TABLE_LEN_RSX 0x3
|
||||
#define ZPCI_TABLE_LEN_RTX 0x3
|
||||
|
||||
#define ZPCI_TABLE_OFFSET_MASK 0xc0
|
||||
#define ZPCI_TABLE_SIZE 0x4000
|
||||
#define ZPCI_TABLE_ALIGN ZPCI_TABLE_SIZE
|
||||
#define ZPCI_TABLE_ENTRY_SIZE (sizeof(unsigned long))
|
||||
#define ZPCI_TABLE_ENTRIES (ZPCI_TABLE_SIZE / ZPCI_TABLE_ENTRY_SIZE)
|
||||
|
||||
#define ZPCI_TABLE_BITS 11
|
||||
#define ZPCI_PT_BITS 8
|
||||
#define ZPCI_ST_SHIFT (ZPCI_PT_BITS + PAGE_SHIFT)
|
||||
#define ZPCI_RT_SHIFT (ZPCI_ST_SHIFT + ZPCI_TABLE_BITS)
|
||||
|
||||
#define ZPCI_RTE_FLAG_MASK 0x3fffULL
|
||||
#define ZPCI_RTE_ADDR_MASK (~ZPCI_RTE_FLAG_MASK)
|
||||
#define ZPCI_STE_FLAG_MASK 0x7ffULL
|
||||
#define ZPCI_STE_ADDR_MASK (~ZPCI_STE_FLAG_MASK)
|
||||
|
||||
/* I/O Page tables */
|
||||
#define ZPCI_PTE_VALID_MASK 0x400
|
||||
#define ZPCI_PTE_INVALID 0x400
|
||||
#define ZPCI_PTE_VALID 0x000
|
||||
#define ZPCI_PT_SIZE 0x800
|
||||
#define ZPCI_PT_ALIGN ZPCI_PT_SIZE
|
||||
#define ZPCI_PT_ENTRIES (ZPCI_PT_SIZE / ZPCI_TABLE_ENTRY_SIZE)
|
||||
#define ZPCI_PT_MASK (ZPCI_PT_ENTRIES - 1)
|
||||
|
||||
#define ZPCI_PTE_FLAG_MASK 0xfffULL
|
||||
#define ZPCI_PTE_ADDR_MASK (~ZPCI_PTE_FLAG_MASK)
|
||||
|
||||
/* Shared bits */
|
||||
#define ZPCI_TABLE_VALID 0x00
|
||||
#define ZPCI_TABLE_INVALID 0x20
|
||||
#define ZPCI_TABLE_PROTECTED 0x200
|
||||
#define ZPCI_TABLE_UNPROTECTED 0x000
|
||||
|
||||
#define ZPCI_TABLE_VALID_MASK 0x20
|
||||
#define ZPCI_TABLE_PROT_MASK 0x200
|
||||
|
||||
typedef struct SeiContainer {
|
||||
QTAILQ_ENTRY(SeiContainer) link;
|
||||
uint32_t fid;
|
||||
uint32_t fh;
|
||||
uint8_t cc;
|
||||
uint16_t pec;
|
||||
uint64_t faddr;
|
||||
uint32_t e;
|
||||
} SeiContainer;
|
||||
|
||||
typedef struct PciCcdfErr {
|
||||
uint32_t reserved1;
|
||||
uint32_t fh;
|
||||
uint32_t fid;
|
||||
uint32_t e;
|
||||
uint64_t faddr;
|
||||
uint32_t reserved3;
|
||||
uint16_t reserved4;
|
||||
uint16_t pec;
|
||||
} QEMU_PACKED PciCcdfErr;
|
||||
|
||||
typedef struct PciCcdfAvail {
|
||||
uint32_t reserved1;
|
||||
uint32_t fh;
|
||||
uint32_t fid;
|
||||
uint32_t reserved2;
|
||||
uint32_t reserved3;
|
||||
uint32_t reserved4;
|
||||
uint32_t reserved5;
|
||||
uint16_t reserved6;
|
||||
uint16_t pec;
|
||||
} QEMU_PACKED PciCcdfAvail;
|
||||
|
||||
typedef struct ChscSeiNt2Res {
|
||||
uint16_t length;
|
||||
uint16_t code;
|
||||
uint16_t reserved1;
|
||||
uint8_t reserved2;
|
||||
uint8_t nt;
|
||||
uint8_t flags;
|
||||
uint8_t reserved3;
|
||||
uint8_t reserved4;
|
||||
uint8_t cc;
|
||||
uint32_t reserved5[13];
|
||||
uint8_t ccdf[4016];
|
||||
} QEMU_PACKED ChscSeiNt2Res;
|
||||
|
||||
typedef struct PciCfgSccb {
|
||||
SCCBHeader header;
|
||||
uint8_t atype;
|
||||
uint8_t reserved1;
|
||||
uint16_t reserved2;
|
||||
uint32_t aid;
|
||||
} QEMU_PACKED PciCfgSccb;
|
||||
|
||||
typedef struct S390MsixInfo {
|
||||
bool available;
|
||||
uint8_t table_bar;
|
||||
uint8_t pba_bar;
|
||||
uint16_t entries;
|
||||
uint32_t table_offset;
|
||||
uint32_t pba_offset;
|
||||
} S390MsixInfo;
|
||||
|
||||
typedef struct S390PCIBusDevice {
|
||||
PCIDevice *pdev;
|
||||
bool configured;
|
||||
bool error_state;
|
||||
bool lgstg_blocked;
|
||||
uint32_t fh;
|
||||
uint32_t fid;
|
||||
uint64_t g_iota;
|
||||
uint64_t pba;
|
||||
uint64_t pal;
|
||||
uint64_t fmb_addr;
|
||||
uint8_t isc;
|
||||
uint16_t noi;
|
||||
uint8_t sum;
|
||||
S390MsixInfo msix;
|
||||
AdapterRoutes routes;
|
||||
AddressSpace as;
|
||||
MemoryRegion mr;
|
||||
} S390PCIBusDevice;
|
||||
|
||||
typedef struct S390pciState {
|
||||
PCIHostState parent_obj;
|
||||
S390PCIBusDevice pbdev[PCI_SLOT_MAX];
|
||||
AddressSpace msix_notify_as;
|
||||
MemoryRegion msix_notify_mr;
|
||||
QTAILQ_HEAD(, SeiContainer) pending_sei;
|
||||
} S390pciState;
|
||||
|
||||
int chsc_sei_nt2_get_event(void *res);
|
||||
int chsc_sei_nt2_have_event(void);
|
||||
void s390_pci_sclp_configure(int configure, SCCB *sccb);
|
||||
S390PCIBusDevice *s390_pci_find_dev_by_idx(uint32_t idx);
|
||||
S390PCIBusDevice *s390_pci_find_dev_by_fh(uint32_t fh);
|
||||
S390PCIBusDevice *s390_pci_find_dev_by_fid(uint32_t fid);
|
||||
|
||||
#endif
|
||||
@ -18,6 +18,7 @@
|
||||
#include "css.h"
|
||||
#include "virtio-ccw.h"
|
||||
#include "qemu/config-file.h"
|
||||
#include "s390-pci-bus.h"
|
||||
|
||||
#define TYPE_S390_CCW_MACHINE "s390-ccw-machine"
|
||||
|
||||
@ -91,6 +92,7 @@ static void ccw_init(MachineState *machine)
|
||||
uint8_t *storage_keys;
|
||||
int ret;
|
||||
VirtualCssBus *css_bus;
|
||||
DeviceState *dev;
|
||||
QemuOpts *opts = qemu_opts_find(qemu_find_opts("memory"), NULL);
|
||||
ram_addr_t pad_size = 0;
|
||||
ram_addr_t maxmem = qemu_opt_get_size(opts, "maxmem", my_ram_size);
|
||||
@ -127,6 +129,11 @@ static void ccw_init(MachineState *machine)
|
||||
machine->initrd_filename, "s390-ccw.img");
|
||||
s390_flic_init();
|
||||
|
||||
dev = qdev_create(NULL, TYPE_S390_PCI_HOST_BRIDGE);
|
||||
object_property_add_child(qdev_get_machine(), TYPE_S390_PCI_HOST_BRIDGE,
|
||||
OBJECT(dev), NULL);
|
||||
qdev_init_nofail(dev);
|
||||
|
||||
/* register hypercalls */
|
||||
virtio_ccw_register_hcalls();
|
||||
|
||||
|
||||
@ -20,6 +20,7 @@
|
||||
#include "qemu/config-file.h"
|
||||
#include "hw/s390x/sclp.h"
|
||||
#include "hw/s390x/event-facility.h"
|
||||
#include "hw/s390x/s390-pci-bus.h"
|
||||
|
||||
static inline SCLPEventFacility *get_event_facility(void)
|
||||
{
|
||||
@ -62,7 +63,8 @@ static void read_SCP_info(SCCB *sccb)
|
||||
read_info->entries[i].type = 0;
|
||||
}
|
||||
|
||||
read_info->facilities = cpu_to_be64(SCLP_HAS_CPU_INFO);
|
||||
read_info->facilities = cpu_to_be64(SCLP_HAS_CPU_INFO |
|
||||
SCLP_HAS_PCI_RECONFIG);
|
||||
|
||||
/*
|
||||
* The storage increment size is a multiple of 1M and is a power of 2.
|
||||
@ -350,6 +352,12 @@ static void sclp_execute(SCCB *sccb, uint32_t code)
|
||||
case SCLP_UNASSIGN_STORAGE:
|
||||
unassign_storage(sccb);
|
||||
break;
|
||||
case SCLP_CMDW_CONFIGURE_PCI:
|
||||
s390_pci_sclp_configure(1, sccb);
|
||||
break;
|
||||
case SCLP_CMDW_DECONFIGURE_PCI:
|
||||
s390_pci_sclp_configure(0, sccb);
|
||||
break;
|
||||
default:
|
||||
efc->command_handler(ef, sccb, code);
|
||||
break;
|
||||
|
||||
@ -43,14 +43,22 @@
|
||||
#define SCLP_CMDW_CONFIGURE_CPU 0x00110001
|
||||
#define SCLP_CMDW_DECONFIGURE_CPU 0x00100001
|
||||
|
||||
/* SCLP PCI codes */
|
||||
#define SCLP_HAS_PCI_RECONFIG 0x0000000040000000ULL
|
||||
#define SCLP_CMDW_CONFIGURE_PCI 0x001a0001
|
||||
#define SCLP_CMDW_DECONFIGURE_PCI 0x001b0001
|
||||
#define SCLP_RECONFIG_PCI_ATPYE 2
|
||||
|
||||
/* SCLP response codes */
|
||||
#define SCLP_RC_NORMAL_READ_COMPLETION 0x0010
|
||||
#define SCLP_RC_NORMAL_COMPLETION 0x0020
|
||||
#define SCLP_RC_SCCB_BOUNDARY_VIOLATION 0x0100
|
||||
#define SCLP_RC_NO_ACTION_REQUIRED 0x0120
|
||||
#define SCLP_RC_INVALID_SCLP_COMMAND 0x01f0
|
||||
#define SCLP_RC_CONTAINED_EQUIPMENT_CHECK 0x0340
|
||||
#define SCLP_RC_INSUFFICIENT_SCCB_LENGTH 0x0300
|
||||
#define SCLP_RC_STANDBY_READ_COMPLETION 0x0410
|
||||
#define SCLP_RC_ADAPTER_ID_NOT_RECOGNIZED 0x09f0
|
||||
#define SCLP_RC_INVALID_FUNCTION 0x40f0
|
||||
#define SCLP_RC_NO_EVENT_BUFFERS_STORED 0x60f0
|
||||
#define SCLP_RC_INVALID_SELECTION_MASK 0x70f0
|
||||
|
||||
@ -14,6 +14,7 @@
|
||||
#include "cpu.h"
|
||||
#include "ioinst.h"
|
||||
#include "trace.h"
|
||||
#include "hw/s390x/s390-pci-bus.h"
|
||||
|
||||
int ioinst_disassemble_sch_ident(uint32_t value, int *m, int *cssid, int *ssid,
|
||||
int *schid)
|
||||
@ -398,6 +399,7 @@ typedef struct ChscResp {
|
||||
#define CHSC_SCPD 0x0002
|
||||
#define CHSC_SCSC 0x0010
|
||||
#define CHSC_SDA 0x0031
|
||||
#define CHSC_SEI 0x000e
|
||||
|
||||
#define CHSC_SCPD_0_M 0x20000000
|
||||
#define CHSC_SCPD_0_C 0x10000000
|
||||
@ -566,6 +568,53 @@ out:
|
||||
res->param = 0;
|
||||
}
|
||||
|
||||
static int chsc_sei_nt0_get_event(void *res)
|
||||
{
|
||||
/* no events yet */
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int chsc_sei_nt0_have_event(void)
|
||||
{
|
||||
/* no events yet */
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define CHSC_SEI_NT0 (1ULL << 63)
|
||||
#define CHSC_SEI_NT2 (1ULL << 61)
|
||||
static void ioinst_handle_chsc_sei(ChscReq *req, ChscResp *res)
|
||||
{
|
||||
uint64_t selection_mask = ldq_p(&req->param1);
|
||||
uint8_t *res_flags = (uint8_t *)res->data;
|
||||
int have_event = 0;
|
||||
int have_more = 0;
|
||||
|
||||
/* regarding architecture nt0 can not be masked */
|
||||
have_event = !chsc_sei_nt0_get_event(res);
|
||||
have_more = chsc_sei_nt0_have_event();
|
||||
|
||||
if (selection_mask & CHSC_SEI_NT2) {
|
||||
if (!have_event) {
|
||||
have_event = !chsc_sei_nt2_get_event(res);
|
||||
}
|
||||
|
||||
if (!have_more) {
|
||||
have_more = chsc_sei_nt2_have_event();
|
||||
}
|
||||
}
|
||||
|
||||
if (have_event) {
|
||||
res->code = cpu_to_be16(0x0001);
|
||||
if (have_more) {
|
||||
(*res_flags) |= 0x80;
|
||||
} else {
|
||||
(*res_flags) &= ~0x80;
|
||||
}
|
||||
} else {
|
||||
res->code = cpu_to_be16(0x0004);
|
||||
}
|
||||
}
|
||||
|
||||
static void ioinst_handle_chsc_unimplemented(ChscResp *res)
|
||||
{
|
||||
res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
|
||||
@ -617,6 +666,9 @@ void ioinst_handle_chsc(S390CPU *cpu, uint32_t ipb)
|
||||
case CHSC_SDA:
|
||||
ioinst_handle_chsc_sda(req, res);
|
||||
break;
|
||||
case CHSC_SEI:
|
||||
ioinst_handle_chsc_sei(req, res);
|
||||
break;
|
||||
default:
|
||||
ioinst_handle_chsc_unimplemented(res);
|
||||
break;
|
||||
|
||||
@ -204,6 +204,7 @@ typedef struct CRW {
|
||||
|
||||
#define CRW_RSC_SUBCH 0x3
|
||||
#define CRW_RSC_CHP 0x4
|
||||
#define CRW_RSC_CSS 0xb
|
||||
|
||||
/* I/O interruption code */
|
||||
typedef struct IOIntCode {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user