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target-arm: Implement MRS (banked) and MSR (banked) instructions
Starting with the ARMv7 Virtualization Extensions, the A32 and T32 instruction sets provide instructions "MSR (banked)" and "MRS (banked)" which can be used to access registers for a mode other than the current one: * R<m>_<mode> * ELR_hyp * SPSR_<mode> Implement the missing instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1456762734-23939-1-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
f09f9bd9fa
commit
8bfd0550be
@ -77,6 +77,9 @@ DEF_HELPER_1(exception_return, void, env)
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DEF_HELPER_2(get_r13_banked, i32, env, i32)
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DEF_HELPER_3(set_r13_banked, void, env, i32, i32)
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DEF_HELPER_3(mrs_banked, i32, env, i32, i32)
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DEF_HELPER_4(msr_banked, void, env, i32, i32, i32)
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DEF_HELPER_2(get_user_reg, i32, env, i32)
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DEF_HELPER_3(set_user_reg, void, env, i32, i32)
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@ -494,6 +494,126 @@ uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
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}
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}
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static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode,
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uint32_t regno)
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{
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/* Raise an exception if the requested access is one of the UNPREDICTABLE
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* cases; otherwise return. This broadly corresponds to the pseudocode
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* BankedRegisterAccessValid() and SPSRAccessValid(),
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* except that we have already handled some cases at translate time.
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*/
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int curmode = env->uncached_cpsr & CPSR_M;
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if (curmode == tgtmode) {
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goto undef;
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}
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if (tgtmode == ARM_CPU_MODE_USR) {
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switch (regno) {
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case 8 ... 12:
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if (curmode != ARM_CPU_MODE_FIQ) {
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goto undef;
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}
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break;
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case 13:
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if (curmode == ARM_CPU_MODE_SYS) {
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goto undef;
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}
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break;
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case 14:
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if (curmode == ARM_CPU_MODE_HYP || curmode == ARM_CPU_MODE_SYS) {
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goto undef;
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}
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break;
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default:
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break;
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}
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}
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if (tgtmode == ARM_CPU_MODE_HYP) {
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switch (regno) {
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case 17: /* ELR_Hyp */
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if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) {
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goto undef;
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}
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break;
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default:
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if (curmode != ARM_CPU_MODE_MON) {
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goto undef;
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}
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break;
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}
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}
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return;
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undef:
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raise_exception(env, EXCP_UDEF, syn_uncategorized(),
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exception_target_el(env));
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}
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void HELPER(msr_banked)(CPUARMState *env, uint32_t value, uint32_t tgtmode,
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uint32_t regno)
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{
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msr_mrs_banked_exc_checks(env, tgtmode, regno);
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switch (regno) {
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case 16: /* SPSRs */
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env->banked_spsr[bank_number(tgtmode)] = value;
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break;
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case 17: /* ELR_Hyp */
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env->elr_el[2] = value;
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break;
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case 13:
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env->banked_r13[bank_number(tgtmode)] = value;
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break;
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case 14:
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env->banked_r14[bank_number(tgtmode)] = value;
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break;
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case 8 ... 12:
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switch (tgtmode) {
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case ARM_CPU_MODE_USR:
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env->usr_regs[regno - 8] = value;
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break;
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case ARM_CPU_MODE_FIQ:
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env->fiq_regs[regno - 8] = value;
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break;
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default:
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g_assert_not_reached();
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}
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break;
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default:
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g_assert_not_reached();
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}
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}
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uint32_t HELPER(mrs_banked)(CPUARMState *env, uint32_t tgtmode, uint32_t regno)
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{
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msr_mrs_banked_exc_checks(env, tgtmode, regno);
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switch (regno) {
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case 16: /* SPSRs */
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return env->banked_spsr[bank_number(tgtmode)];
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case 17: /* ELR_Hyp */
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return env->elr_el[2];
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case 13:
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return env->banked_r13[bank_number(tgtmode)];
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case 14:
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return env->banked_r14[bank_number(tgtmode)];
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case 8 ... 12:
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switch (tgtmode) {
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case ARM_CPU_MODE_USR:
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return env->usr_regs[regno - 8];
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case ARM_CPU_MODE_FIQ:
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return env->fiq_regs[regno - 8];
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default:
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g_assert_not_reached();
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}
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default:
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g_assert_not_reached();
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}
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}
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void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
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uint32_t isread)
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{
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@ -4160,6 +4160,195 @@ static int gen_set_psr_im(DisasContext *s, uint32_t mask, int spsr, uint32_t val
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return gen_set_psr(s, mask, spsr, tmp);
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}
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static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
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int *tgtmode, int *regno)
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{
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/* Decode the r and sysm fields of MSR/MRS banked accesses into
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* the target mode and register number, and identify the various
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* unpredictable cases.
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* MSR (banked) and MRS (banked) are CONSTRAINED UNPREDICTABLE if:
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* + executed in user mode
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* + using R15 as the src/dest register
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* + accessing an unimplemented register
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* + accessing a register that's inaccessible at current PL/security state*
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* + accessing a register that you could access with a different insn
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* We choose to UNDEF in all these cases.
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* Since we don't know which of the various AArch32 modes we are in
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* we have to defer some checks to runtime.
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* Accesses to Monitor mode registers from Secure EL1 (which implies
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* that EL3 is AArch64) must trap to EL3.
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*
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* If the access checks fail this function will emit code to take
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* an exception and return false. Otherwise it will return true,
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* and set *tgtmode and *regno appropriately.
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*/
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int exc_target = default_exception_el(s);
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/* These instructions are present only in ARMv8, or in ARMv7 with the
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* Virtualization Extensions.
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*/
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if (!arm_dc_feature(s, ARM_FEATURE_V8) &&
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!arm_dc_feature(s, ARM_FEATURE_EL2)) {
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goto undef;
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}
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if (IS_USER(s) || rn == 15) {
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goto undef;
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}
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/* The table in the v8 ARM ARM section F5.2.3 describes the encoding
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* of registers into (r, sysm).
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*/
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if (r) {
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/* SPSRs for other modes */
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switch (sysm) {
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case 0xe: /* SPSR_fiq */
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*tgtmode = ARM_CPU_MODE_FIQ;
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break;
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case 0x10: /* SPSR_irq */
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*tgtmode = ARM_CPU_MODE_IRQ;
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break;
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case 0x12: /* SPSR_svc */
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*tgtmode = ARM_CPU_MODE_SVC;
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break;
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case 0x14: /* SPSR_abt */
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*tgtmode = ARM_CPU_MODE_ABT;
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break;
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case 0x16: /* SPSR_und */
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*tgtmode = ARM_CPU_MODE_UND;
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break;
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case 0x1c: /* SPSR_mon */
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*tgtmode = ARM_CPU_MODE_MON;
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break;
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case 0x1e: /* SPSR_hyp */
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*tgtmode = ARM_CPU_MODE_HYP;
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break;
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default: /* unallocated */
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goto undef;
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}
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/* We arbitrarily assign SPSR a register number of 16. */
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*regno = 16;
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} else {
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/* general purpose registers for other modes */
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switch (sysm) {
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case 0x0 ... 0x6: /* 0b00xxx : r8_usr ... r14_usr */
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*tgtmode = ARM_CPU_MODE_USR;
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*regno = sysm + 8;
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break;
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case 0x8 ... 0xe: /* 0b01xxx : r8_fiq ... r14_fiq */
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*tgtmode = ARM_CPU_MODE_FIQ;
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*regno = sysm;
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break;
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case 0x10 ... 0x11: /* 0b1000x : r14_irq, r13_irq */
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*tgtmode = ARM_CPU_MODE_IRQ;
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*regno = sysm & 1 ? 13 : 14;
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break;
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case 0x12 ... 0x13: /* 0b1001x : r14_svc, r13_svc */
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*tgtmode = ARM_CPU_MODE_SVC;
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*regno = sysm & 1 ? 13 : 14;
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break;
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case 0x14 ... 0x15: /* 0b1010x : r14_abt, r13_abt */
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*tgtmode = ARM_CPU_MODE_ABT;
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*regno = sysm & 1 ? 13 : 14;
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break;
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case 0x16 ... 0x17: /* 0b1011x : r14_und, r13_und */
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*tgtmode = ARM_CPU_MODE_UND;
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*regno = sysm & 1 ? 13 : 14;
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break;
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case 0x1c ... 0x1d: /* 0b1110x : r14_mon, r13_mon */
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*tgtmode = ARM_CPU_MODE_MON;
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*regno = sysm & 1 ? 13 : 14;
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break;
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case 0x1e ... 0x1f: /* 0b1111x : elr_hyp, r13_hyp */
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*tgtmode = ARM_CPU_MODE_HYP;
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/* Arbitrarily pick 17 for ELR_Hyp (which is not a banked LR!) */
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*regno = sysm & 1 ? 13 : 17;
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break;
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default: /* unallocated */
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goto undef;
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}
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}
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/* Catch the 'accessing inaccessible register' cases we can detect
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* at translate time.
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*/
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switch (*tgtmode) {
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case ARM_CPU_MODE_MON:
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if (!arm_dc_feature(s, ARM_FEATURE_EL3) || s->ns) {
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goto undef;
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}
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if (s->current_el == 1) {
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/* If we're in Secure EL1 (which implies that EL3 is AArch64)
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* then accesses to Mon registers trap to EL3
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*/
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exc_target = 3;
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goto undef;
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}
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break;
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case ARM_CPU_MODE_HYP:
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/* Note that we can forbid accesses from EL2 here because they
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* must be from Hyp mode itself
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*/
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if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 3) {
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goto undef;
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}
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break;
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default:
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break;
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}
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return true;
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undef:
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/* If we get here then some access check did not pass */
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gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), exc_target);
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return false;
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}
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static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
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{
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TCGv_i32 tcg_reg, tcg_tgtmode, tcg_regno;
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int tgtmode = 0, regno = 0;
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if (!msr_banked_access_decode(s, r, sysm, rn, &tgtmode, ®no)) {
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return;
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}
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/* Sync state because msr_banked() can raise exceptions */
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gen_set_condexec(s);
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gen_set_pc_im(s, s->pc - 4);
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tcg_reg = load_reg(s, rn);
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tcg_tgtmode = tcg_const_i32(tgtmode);
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tcg_regno = tcg_const_i32(regno);
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gen_helper_msr_banked(cpu_env, tcg_reg, tcg_tgtmode, tcg_regno);
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tcg_temp_free_i32(tcg_tgtmode);
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tcg_temp_free_i32(tcg_regno);
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tcg_temp_free_i32(tcg_reg);
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s->is_jmp = DISAS_UPDATE;
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}
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static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
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{
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TCGv_i32 tcg_reg, tcg_tgtmode, tcg_regno;
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int tgtmode = 0, regno = 0;
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if (!msr_banked_access_decode(s, r, sysm, rn, &tgtmode, ®no)) {
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return;
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}
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/* Sync state because mrs_banked() can raise exceptions */
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gen_set_condexec(s);
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gen_set_pc_im(s, s->pc - 4);
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tcg_reg = tcg_temp_new_i32();
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tcg_tgtmode = tcg_const_i32(tgtmode);
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tcg_regno = tcg_const_i32(regno);
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gen_helper_mrs_banked(tcg_reg, cpu_env, tcg_tgtmode, tcg_regno);
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tcg_temp_free_i32(tcg_tgtmode);
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tcg_temp_free_i32(tcg_regno);
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store_reg(s, rn, tcg_reg);
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s->is_jmp = DISAS_UPDATE;
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}
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/* Generate an old-style exception return. Marks pc as dead. */
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static void gen_exception_return(DisasContext *s, TCGv_i32 pc)
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{
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@ -8022,7 +8211,26 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
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sh = (insn >> 4) & 0xf;
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rm = insn & 0xf;
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switch (sh) {
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case 0x0: /* move program status register */
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case 0x0: /* MSR, MRS */
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if (insn & (1 << 9)) {
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/* MSR (banked) and MRS (banked) */
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int sysm = extract32(insn, 16, 4) |
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(extract32(insn, 8, 1) << 4);
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int r = extract32(insn, 22, 1);
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if (op1 & 1) {
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/* MSR (banked) */
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gen_msr_banked(s, r, sysm, rm);
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} else {
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/* MRS (banked) */
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int rd = extract32(insn, 12, 4);
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gen_mrs_banked(s, r, sysm, rd);
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}
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break;
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}
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/* MSR, MRS (for PSRs) */
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if (op1 & 1) {
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/* PSR = reg */
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tmp = load_reg(s, rm);
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@ -10133,6 +10341,18 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
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if (arm_dc_feature(s, ARM_FEATURE_M)) {
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goto illegal_op;
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}
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if (extract32(insn, 5, 1)) {
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/* MSR (banked) */
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int sysm = extract32(insn, 8, 4) |
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(extract32(insn, 4, 1) << 4);
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int r = op & 1;
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gen_msr_banked(s, r, sysm, rm);
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break;
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}
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/* MSR (for PSRs) */
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tmp = load_reg(s, rn);
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if (gen_set_psr(s,
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msr_mask(s, (insn >> 8) & 0xf, op == 1),
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@ -10205,7 +10425,17 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
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tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
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gen_exception_return(s, tmp);
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break;
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case 6: /* mrs cpsr. */
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case 6: /* MRS */
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if (extract32(insn, 5, 1)) {
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/* MRS (banked) */
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int sysm = extract32(insn, 16, 4) |
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(extract32(insn, 4, 1) << 4);
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gen_mrs_banked(s, 0, sysm, rd);
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break;
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}
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/* mrs cpsr */
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tmp = tcg_temp_new_i32();
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if (arm_dc_feature(s, ARM_FEATURE_M)) {
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addr = tcg_const_i32(insn & 0xff);
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@ -10216,7 +10446,17 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
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}
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store_reg(s, rd, tmp);
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break;
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case 7: /* mrs spsr. */
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case 7: /* MRS */
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if (extract32(insn, 5, 1)) {
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/* MRS (banked) */
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int sysm = extract32(insn, 16, 4) |
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(extract32(insn, 4, 1) << 4);
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gen_mrs_banked(s, 1, sysm, rd);
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break;
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}
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/* mrs spsr. */
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/* Not accessible in user mode. */
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if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) {
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goto illegal_op;
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