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hw/riscv: Connect Shakti UART to Shakti platform

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Connect one shakti uart to the shakti_c machine.

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210401181457.73039-5-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Vijai Kumar K 2021-04-01 23:44:57 +05:30 committed by Alistair Francis
parent 07f334d89d
commit 8a2aca3d79
2 changed files with 10 additions and 0 deletions
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8
hw/riscv/shakti_c.c
View File

@ -128,6 +128,13 @@ static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
SIFIVE_CLINT_TIMEBASE_FREQ, false);
qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0));
if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&sss->uart), 0,
shakti_c_memmap[SHAKTI_C_UART].base);
/* ROM */
memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
@ -146,6 +153,7 @@ static void shakti_c_soc_instance_init(Object *obj)
ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
object_initialize_child(obj, "uart", &sss->uart, TYPE_SHAKTI_UART);
/*
* CPU type is fixed and we are not supporting passing from commandline yet.

2
include/hw/riscv/shakti_c.h
View File

@ -21,6 +21,7 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/boards.h"
#include "hw/char/shakti_uart.h"
#define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
#define RISCV_SHAKTI_SOC(obj) \
@ -33,6 +34,7 @@ typedef struct ShaktiCSoCState {
/*< public >*/
RISCVHartArrayState cpus;
DeviceState *plic;
ShaktiUartState uart;
MemoryRegion rom;
} ShaktiCSoCState;