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Hexagon (target/hexagon) cleanup gen_store_conditional[48] functions

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Previously the store-conditional code was writing to hex_pred[prednum].
Then, the fGEN_TCG override was reading from there to the destination
variable so that the packet commit logic would handle it properly.

The correct implementation is to write to the destination variable
and don't have the extra read in the override.

Remove the unused arguments from gen_store_conditional[48]

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1622589584-22571-4-git-send-email-tsimpson@quicinc.com>
This commit is contained in:
Taylor Simpson 2021-06-01 18:19:43 -05:00
parent a5a8d98c85
commit 8872533671
3 changed files with 7 additions and 16 deletions
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4
target/hexagon/gen_tcg.h
View File

@ -424,9 +424,9 @@
#define fGEN_TCG_L4_loadd_locked(SHORTCODE) \
SHORTCODE
#define fGEN_TCG_S2_storew_locked(SHORTCODE) \
do { SHORTCODE; READ_PREG(PdV, PdN); } while (0)
SHORTCODE
#define fGEN_TCG_S4_stored_locked(SHORTCODE) \
do { SHORTCODE; READ_PREG(PdV, PdN); } while (0)
SHORTCODE
#define fGEN_TCG_STORE(SHORTCODE) \
do { \

16
target/hexagon/genptr.c
View File

@ -27,12 +27,6 @@
#undef QEMU_GENERATE
#include "gen_tcg.h"
static inline TCGv gen_read_preg(TCGv pred, uint8_t num)
{
tcg_gen_mov_tl(pred, hex_pred[num]);
return pred;
}
static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot)
{
TCGv zero = tcg_const_tl(0);
@ -334,8 +328,7 @@ static inline void gen_load_locked8u(TCGv_i64 dest, TCGv vaddr, int mem_index)
tcg_gen_mov_i64(hex_llsc_val_i64, dest);
}
static inline void gen_store_conditional4(CPUHexagonState *env,
DisasContext *ctx, int prednum,
static inline void gen_store_conditional4(DisasContext *ctx,
TCGv pred, TCGv vaddr, TCGv src)
{
TCGLabel *fail = gen_new_label();
@ -349,7 +342,7 @@ static inline void gen_store_conditional4(CPUHexagonState *env,
tmp = tcg_temp_new();
tcg_gen_atomic_cmpxchg_tl(tmp, hex_llsc_addr, hex_llsc_val, src,
ctx->mem_idx, MO_32);
tcg_gen_movcond_tl(TCG_COND_EQ, hex_pred[prednum], tmp, hex_llsc_val,
tcg_gen_movcond_tl(TCG_COND_EQ, pred, tmp, hex_llsc_val,
one, zero);
tcg_temp_free(one);
tcg_temp_free(zero);
@ -363,8 +356,7 @@ static inline void gen_store_conditional4(CPUHexagonState *env,
tcg_gen_movi_tl(hex_llsc_addr, ~0);
}
static inline void gen_store_conditional8(CPUHexagonState *env,
DisasContext *ctx, int prednum,
static inline void gen_store_conditional8(DisasContext *ctx,
TCGv pred, TCGv vaddr, TCGv_i64 src)
{
TCGLabel *fail = gen_new_label();
@ -380,7 +372,7 @@ static inline void gen_store_conditional8(CPUHexagonState *env,
ctx->mem_idx, MO_64);
tcg_gen_movcond_i64(TCG_COND_EQ, tmp, tmp, hex_llsc_val_i64,
one, zero);
tcg_gen_extrl_i64_i32(hex_pred[prednum], tmp);
tcg_gen_extrl_i64_i32(pred, tmp);
tcg_temp_free_i64(one);
tcg_temp_free_i64(zero);
tcg_temp_free_i64(tmp);

3
target/hexagon/macros.h
View File

@ -24,7 +24,6 @@
#ifdef QEMU_GENERATE
#define READ_REG(dest, NUM) gen_read_reg(dest, NUM)
#define READ_PREG(dest, NUM) gen_read_preg(dest, (NUM))
#else
#define READ_REG(NUM) (env->gpr[(NUM)])
#define READ_PREG(NUM) (env->pred[NUM])
@ -591,7 +590,7 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
#ifdef QEMU_GENERATE
#define fSTORE_LOCKED(NUM, SIZE, EA, SRC, PRED) \
gen_store_conditional##SIZE(env, ctx, PdN, PRED, EA, SRC);
gen_store_conditional##SIZE(ctx, PRED, EA, SRC);
#endif
#ifdef QEMU_GENERATE