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https://github.com/qemu/qemu.git
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target-arm queue:
* enable FEAT_RNG on Neoverse-N2 * hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZ * Fix SME FMOPA (16-bit), BFMOPA * hw/core/machine: Constify MachineClass::valid_cpu_types[] * stm32f* machines: Report error when user asks for wrong CPU type * hw/arm/fsl-imx: Do not ignore Error argument -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmVchLYZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3kHMD/47tKxzrsXc6+V9esRQGi2H 1hAgLBwglEdxLXokF+Di41sh/fvK7wYVXO/hiWlq+9h3kG3D/u1N5r1TdMPMUb9j 4Sg3rOejn7nzkxVZ6MZ/K/1j84C9bfrt4sboVHZVRvWuvbiyuTuivEr4IqLYO4x3 AIwhFMQ5gbNrmClZh/DBxj0keO13cp63Fg2JSSICdi+1Dw9rRXTyhJloMu1omeqc k/BXzjSeNXpLSMyGWBR3uaPcJBaGC1xnz3Z1V7fUY1EYD2Cu1oo5lEZ9aNO5t30d XW/qVGLa3b1Cb7WuEO247RnU3N2oZotozjFtdj/8IQoYWspM9RHyipEimUlegVdO 3fpu8QGsN1ljNiwjdk0i6OwS7SGxcPtteFOaqEf/Yogj4EOKTn/Rx5TT4vJ5DhmI 2w/9J15JWDIE1paNwecuFWbxCOOzSsOtSxzuyLSZDU3GlNfJ4zoF6YboROLYfejy NXZABFhGd/0ykX7r0VY1GGYXUQ+akv6q+VDmVZCP9gMiRUiqmFPwMLMLlcuHb8G5 8UztN5SvOG2EYXj28Zx0BnGCNiGdI15rWMb0veqAtbnn3yEdltW3O475BAhZ0PB7 OVpLWnXwmWURm/BGlwb1PH5s3kgWgzOebcBgcnCftwFQ8EedQAQDA5FmT+nK5SfV VoOf89PngTubU6B3BOfeBw== =thIa -----END PGP SIGNATURE----- Merge tag 'pull-target-arm-20231121' of https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * enable FEAT_RNG on Neoverse-N2 * hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZ * Fix SME FMOPA (16-bit), BFMOPA * hw/core/machine: Constify MachineClass::valid_cpu_types[] * stm32f* machines: Report error when user asks for wrong CPU type * hw/arm/fsl-imx: Do not ignore Error argument # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmVchLYZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3kHMD/47tKxzrsXc6+V9esRQGi2H # 1hAgLBwglEdxLXokF+Di41sh/fvK7wYVXO/hiWlq+9h3kG3D/u1N5r1TdMPMUb9j # 4Sg3rOejn7nzkxVZ6MZ/K/1j84C9bfrt4sboVHZVRvWuvbiyuTuivEr4IqLYO4x3 # AIwhFMQ5gbNrmClZh/DBxj0keO13cp63Fg2JSSICdi+1Dw9rRXTyhJloMu1omeqc # k/BXzjSeNXpLSMyGWBR3uaPcJBaGC1xnz3Z1V7fUY1EYD2Cu1oo5lEZ9aNO5t30d # XW/qVGLa3b1Cb7WuEO247RnU3N2oZotozjFtdj/8IQoYWspM9RHyipEimUlegVdO # 3fpu8QGsN1ljNiwjdk0i6OwS7SGxcPtteFOaqEf/Yogj4EOKTn/Rx5TT4vJ5DhmI # 2w/9J15JWDIE1paNwecuFWbxCOOzSsOtSxzuyLSZDU3GlNfJ4zoF6YboROLYfejy # NXZABFhGd/0ykX7r0VY1GGYXUQ+akv6q+VDmVZCP9gMiRUiqmFPwMLMLlcuHb8G5 # 8UztN5SvOG2EYXj28Zx0BnGCNiGdI15rWMb0veqAtbnn3yEdltW3O475BAhZ0PB7 # OVpLWnXwmWURm/BGlwb1PH5s3kgWgzOebcBgcnCftwFQ8EedQAQDA5FmT+nK5SfV # VoOf89PngTubU6B3BOfeBw== # =thIa # -----END PGP SIGNATURE----- # gpg: Signature made Tue 21 Nov 2023 05:21:42 EST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20231121' of https://git.linaro.org/people/pmaydell/qemu-arm: hw/arm/fsl-imx: Do not ignore Error argument hw/arm/stm32f100: Report error when incorrect CPU is used hw/arm/stm32f205: Report error when incorrect CPU is used hw/arm/stm32f405: Report error when incorrect CPU is used hw/core/machine: Constify MachineClass::valid_cpu_types[] target/arm: Fix SME FMOPA (16-bit), BFMOPA hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZ target/arm: enable FEAT_RNG on Neoverse-N2 Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
commit
85f1051248
@ -169,7 +169,8 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
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epit_table[i].irq));
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}
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object_property_set_uint(OBJECT(&s->fec), "phy-num", s->phy_num, &err);
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object_property_set_uint(OBJECT(&s->fec), "phy-num", s->phy_num,
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&error_abort);
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qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->fec), errp)) {
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@ -379,7 +379,8 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
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spi_table[i].irq));
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}
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object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num, &err);
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object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num,
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&error_abort);
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qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->eth), errp)) {
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return;
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@ -44,7 +44,6 @@ static void netduino2_init(MachineState *machine)
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clock_set_hz(sysclk, SYSCLK_FRQ);
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dev = qdev_new(TYPE_STM32F205_SOC);
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qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
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qdev_connect_clock_in(dev, "sysclk", sysclk);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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@ -54,8 +53,14 @@ static void netduino2_init(MachineState *machine)
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static void netduino2_machine_init(MachineClass *mc)
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{
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static const char * const valid_cpu_types[] = {
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ARM_CPU_TYPE_NAME("cortex-m3"),
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NULL
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};
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mc->desc = "Netduino 2 Machine (Cortex-M3)";
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mc->init = netduino2_init;
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mc->valid_cpu_types = valid_cpu_types;
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mc->ignore_memory_transaction_failures = true;
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}
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@ -44,7 +44,6 @@ static void netduinoplus2_init(MachineState *machine)
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clock_set_hz(sysclk, SYSCLK_FRQ);
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dev = qdev_new(TYPE_STM32F405_SOC);
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qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
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qdev_connect_clock_in(dev, "sysclk", sysclk);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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@ -55,8 +54,14 @@ static void netduinoplus2_init(MachineState *machine)
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static void netduinoplus2_machine_init(MachineClass *mc)
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{
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static const char * const valid_cpu_types[] = {
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ARM_CPU_TYPE_NAME("cortex-m4"),
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NULL
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};
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mc->desc = "Netduino Plus 2 Machine (Cortex-M4)";
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mc->init = netduinoplus2_init;
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mc->valid_cpu_types = valid_cpu_types;
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}
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DEFINE_MACHINE("netduinoplus2", netduinoplus2_machine_init)
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@ -47,7 +47,6 @@ static void olimex_stm32_h405_init(MachineState *machine)
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clock_set_hz(sysclk, SYSCLK_FRQ);
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dev = qdev_new(TYPE_STM32F405_SOC);
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qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
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qdev_connect_clock_in(dev, "sysclk", sysclk);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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@ -58,9 +57,14 @@ static void olimex_stm32_h405_init(MachineState *machine)
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static void olimex_stm32_h405_machine_init(MachineClass *mc)
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{
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static const char * const valid_cpu_types[] = {
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ARM_CPU_TYPE_NAME("cortex-m4"),
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NULL
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};
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mc->desc = "Olimex STM32-H405 (Cortex-M4)";
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mc->init = olimex_stm32_h405_init;
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mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
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mc->valid_cpu_types = valid_cpu_types;
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/* SRAM pre-allocated as part of the SoC instantiation */
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mc->default_ram_size = 0;
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@ -115,7 +115,7 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
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/* Init ARMv7m */
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armv7m = DEVICE(&s->armv7m);
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qdev_prop_set_uint32(armv7m, "num-irq", 61);
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qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
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qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
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qdev_prop_set_bit(armv7m, "enable-bitband", true);
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qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
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qdev_connect_clock_in(armv7m, "refclk", s->refclk);
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@ -180,17 +180,12 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
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create_unimplemented_device("CRC", 0x40023000, 0x400);
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}
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static Property stm32f100_soc_properties[] = {
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DEFINE_PROP_STRING("cpu-type", STM32F100State, cpu_type),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void stm32f100_soc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = stm32f100_soc_realize;
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device_class_set_props(dc, stm32f100_soc_properties);
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/* No vmstate or reset required: device has no internal state */
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}
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static const TypeInfo stm32f100_soc_info = {
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@ -127,7 +127,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
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armv7m = DEVICE(&s->armv7m);
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qdev_prop_set_uint32(armv7m, "num-irq", 96);
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qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
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qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
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qdev_prop_set_bit(armv7m, "enable-bitband", true);
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qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
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qdev_connect_clock_in(armv7m, "refclk", s->refclk);
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@ -201,17 +201,12 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
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}
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}
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static Property stm32f205_soc_properties[] = {
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DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void stm32f205_soc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = stm32f205_soc_realize;
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device_class_set_props(dc, stm32f205_soc_properties);
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/* No vmstate or reset required: device has no internal state */
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}
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static const TypeInfo stm32f205_soc_info = {
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@ -149,7 +149,7 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
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armv7m = DEVICE(&s->armv7m);
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qdev_prop_set_uint32(armv7m, "num-irq", 96);
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qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
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qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
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qdev_prop_set_bit(armv7m, "enable-bitband", true);
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qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
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qdev_connect_clock_in(armv7m, "refclk", s->refclk);
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@ -287,17 +287,11 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
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create_unimplemented_device("RNG", 0x50060800, 0x400);
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}
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static Property stm32f405_soc_properties[] = {
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DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void stm32f405_soc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = stm32f405_soc_realize;
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device_class_set_props(dc, stm32f405_soc_properties);
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/* No vmstate or reset required: device has no internal state */
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}
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@ -47,7 +47,6 @@ static void stm32vldiscovery_init(MachineState *machine)
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clock_set_hz(sysclk, SYSCLK_FRQ);
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dev = qdev_new(TYPE_STM32F100_SOC);
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qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
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qdev_connect_clock_in(dev, "sysclk", sysclk);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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@ -58,8 +57,14 @@ static void stm32vldiscovery_init(MachineState *machine)
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static void stm32vldiscovery_machine_init(MachineClass *mc)
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{
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static const char * const valid_cpu_types[] = {
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ARM_CPU_TYPE_NAME("cortex-m3"),
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NULL
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};
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mc->desc = "ST STM32VLDISCOVERY (Cortex-M3)";
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mc->init = stm32vldiscovery_init;
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mc->valid_cpu_types = valid_cpu_types;
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}
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DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init)
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@ -672,19 +672,18 @@ static void hppa_nmi(NMIState *n, int cpu_index, Error **errp)
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}
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}
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static const char *HP_B160L_machine_valid_cpu_types[] = {
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TYPE_HPPA_CPU,
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NULL
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};
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static void HP_B160L_machine_init_class_init(ObjectClass *oc, void *data)
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{
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static const char * const valid_cpu_types[] = {
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TYPE_HPPA_CPU,
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NULL
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};
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MachineClass *mc = MACHINE_CLASS(oc);
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NMIClass *nc = NMI_CLASS(oc);
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mc->desc = "HP B160L workstation";
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mc->default_cpu_type = TYPE_HPPA_CPU;
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mc->valid_cpu_types = HP_B160L_machine_valid_cpu_types;
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mc->valid_cpu_types = valid_cpu_types;
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mc->init = machine_HP_B160L_init;
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mc->reset = hppa_machine_reset;
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mc->block_default_type = IF_SCSI;
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@ -709,19 +708,18 @@ static const TypeInfo HP_B160L_machine_init_typeinfo = {
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},
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};
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static const char *HP_C3700_machine_valid_cpu_types[] = {
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TYPE_HPPA64_CPU,
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NULL
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};
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static void HP_C3700_machine_init_class_init(ObjectClass *oc, void *data)
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{
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static const char * const valid_cpu_types[] = {
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TYPE_HPPA64_CPU,
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NULL
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};
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MachineClass *mc = MACHINE_CLASS(oc);
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NMIClass *nc = NMI_CLASS(oc);
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mc->desc = "HP C3700 workstation";
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mc->default_cpu_type = TYPE_HPPA64_CPU;
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mc->valid_cpu_types = HP_C3700_machine_valid_cpu_types;
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mc->valid_cpu_types = valid_cpu_types;
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mc->init = machine_HP_C3700_init;
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mc->reset = hppa_machine_reset;
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mc->block_default_type = IF_SCSI;
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@ -146,7 +146,7 @@ static uint32_t icv_fullprio_mask(GICv3CPUState *cs)
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* with the group priority, whose mask depends on the value of VBPR
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* for the interrupt group.)
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*/
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return ~0U << (8 - cs->vpribits);
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return (~0U << (8 - cs->vpribits)) & 0xff;
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}
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static int ich_highest_active_virt_prio(GICv3CPUState *cs)
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@ -803,7 +803,7 @@ static uint32_t icc_fullprio_mask(GICv3CPUState *cs)
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* with the group priority, whose mask depends on the value of BPR
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* for the interrupt group.)
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*/
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return ~0U << (8 - cs->pribits);
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return (~0U << (8 - cs->pribits)) & 0xff;
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}
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static inline int icc_min_bpr(GICv3CPUState *cs)
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|
@ -726,19 +726,18 @@ static GlobalProperty hw_compat_q800[] = {
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};
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static const size_t hw_compat_q800_len = G_N_ELEMENTS(hw_compat_q800);
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static const char *q800_machine_valid_cpu_types[] = {
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M68K_CPU_TYPE_NAME("m68040"),
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NULL
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};
|
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|
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static void q800_machine_class_init(ObjectClass *oc, void *data)
|
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{
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static const char * const valid_cpu_types[] = {
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M68K_CPU_TYPE_NAME("m68040"),
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NULL
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};
|
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MachineClass *mc = MACHINE_CLASS(oc);
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|
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mc->desc = "Macintosh Quadra 800";
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mc->init = q800_machine_init;
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mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040");
|
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mc->valid_cpu_types = q800_machine_valid_cpu_types;
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mc->valid_cpu_types = valid_cpu_types;
|
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mc->max_cpus = 1;
|
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mc->block_default_type = IF_SCSI;
|
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mc->default_ram_id = "m68k_mac.ram";
|
||||
|
@ -43,12 +43,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC)
|
||||
#define SRAM_SIZE (8 * 1024)
|
||||
|
||||
struct STM32F100State {
|
||||
/*< private >*/
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
/*< public >*/
|
||||
char *cpu_type;
|
||||
|
||||
ARMv7MState armv7m;
|
||||
|
||||
STM32F2XXUsartState usart[STM_NUM_USARTS];
|
||||
|
@ -49,11 +49,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F205State, STM32F205_SOC)
|
||||
#define SRAM_SIZE (128 * 1024)
|
||||
|
||||
struct STM32F205State {
|
||||
/*< private >*/
|
||||
SysBusDevice parent_obj;
|
||||
/*< public >*/
|
||||
|
||||
char *cpu_type;
|
||||
|
||||
ARMv7MState armv7m;
|
||||
|
||||
|
@ -51,11 +51,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F405State, STM32F405_SOC)
|
||||
#define CCM_SIZE (64 * 1024)
|
||||
|
||||
struct STM32F405State {
|
||||
/*< private >*/
|
||||
SysBusDevice parent_obj;
|
||||
/*< public >*/
|
||||
|
||||
char *cpu_type;
|
||||
|
||||
ARMv7MState armv7m;
|
||||
|
||||
|
@ -273,7 +273,7 @@ struct MachineClass {
|
||||
bool has_hotpluggable_cpus;
|
||||
bool ignore_memory_transaction_failures;
|
||||
int numa_mem_align_shift;
|
||||
const char **valid_cpu_types;
|
||||
const char * const *valid_cpu_types;
|
||||
strList *allowed_dynamic_sysbus_devices;
|
||||
bool auto_enable_numa_with_memhp;
|
||||
bool auto_enable_numa_with_memdev;
|
||||
|
@ -1018,7 +1018,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
|
||||
cpu->isar.id_aa64dfr1 = 0;
|
||||
cpu->id_aa64afr0 = 0;
|
||||
cpu->id_aa64afr1 = 0;
|
||||
cpu->isar.id_aa64isar0 = 0x0221111110212120ull; /* with Crypto */
|
||||
cpu->isar.id_aa64isar0 = 0x1221111110212120ull; /* with Crypto and FEAT_RNG */
|
||||
cpu->isar.id_aa64isar1 = 0x0011111101211052ull;
|
||||
cpu->isar.id_aa64mmfr0 = 0x0000022200101125ull;
|
||||
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
|
||||
|
@ -1037,10 +1037,9 @@ void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm, void *vpn,
|
||||
|
||||
m = f16mop_adj_pair(m, pcol, 0);
|
||||
*a = f16_dotadd(*a, n, m, &fpst_std, &fpst_odd);
|
||||
|
||||
col += 4;
|
||||
pcol >>= 4;
|
||||
}
|
||||
col += 4;
|
||||
pcol >>= 4;
|
||||
} while (col & 15);
|
||||
}
|
||||
row += 4;
|
||||
@ -1073,10 +1072,9 @@ void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn,
|
||||
|
||||
m = f16mop_adj_pair(m, pcol, 0);
|
||||
*a = bfdotadd(*a, n, m);
|
||||
|
||||
col += 4;
|
||||
pcol >>= 4;
|
||||
}
|
||||
col += 4;
|
||||
pcol >>= 4;
|
||||
} while (col & 15);
|
||||
}
|
||||
row += 4;
|
||||
|
Loading…
Reference in New Issue
Block a user